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authorFurquan Shaikh <furquan@google.com>2015-03-31 22:59:25 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-22 08:56:36 +0200
commit4b14076fd538348d02c7bdecd17379b421e047c6 (patch)
tree833a3f4305c1610184f43697c4419e97d588c198 /payloads/libpayload
parentfc45f0ba9750b8a7d27d7381a66b6204d66adb60 (diff)
downloadcoreboot-4b14076fd538348d02c7bdecd17379b421e047c6.tar.xz
arm64: Add arch_program_segment_loaded call to arm64
arch_program_segment_loaded ensures that the program segment loaded is synced back from the cache to PoC. dcache_flush_all on arm64 does not guarantee PoC in case of MP systems. Thus, it is important to track and sync back all the required segments using arch_program_segment_loaded. BUG=chrome-os-partner:38231 BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug Change-Id: Ic6fcc7e5e0cccbab317950f8abab0c494041d19a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 284e3784854f764159b64286cea366c66b6bce2c Original-Change-Id: I5c35b9aa2ae9b5c1f2fcdef40ffb1cde7f49cc1a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263327 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9904 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads/libpayload')
-rw-r--r--payloads/libpayload/arch/arm64/cache.c6
-rw-r--r--payloads/libpayload/include/arm64/arch/cache.h3
2 files changed, 9 insertions, 0 deletions
diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c
index 799e2d240c..0755c56731 100644
--- a/payloads/libpayload/arch/arm64/cache.c
+++ b/payloads/libpayload/arch/arm64/cache.c
@@ -122,3 +122,9 @@ void cache_sync_instructions(void)
dcache_clean_all(); /* includes trailing DSB (in assembly) */
icache_invalidate_all(); /* includes leading DSB and trailing ISB */
}
+
+void arch_program_segment_loaded(void const *addr, size_t len)
+{
+ dcache_clean_invalidate_by_mva(addr, len);
+ icache_invalidate_all();
+}
diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h
index 757775886c..7248869111 100644
--- a/payloads/libpayload/include/arm64/arch/cache.h
+++ b/payloads/libpayload/include/arm64/arch/cache.h
@@ -100,6 +100,9 @@ void dcache_mmu_enable(void);
/* perform all icache/dcache maintenance needed after loading new code */
void cache_sync_instructions(void);
+/* Ensure that loaded program segment is synced back from cache to PoC */
+void arch_program_segment_loaded(void const *addr, size_t len);
+
/* tlb invalidate all */
void tlb_invalidate_all(void);