diff options
| author | Julius Werner <jwerner@chromium.org> | 2015-04-21 14:32:36 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2017-05-30 22:17:57 +0200 |
| commit | baa3e70084bac00885667b20efde3e69901cda70 (patch) | |
| tree | ceea5f55a386f4d94ff16fd203aa2191a8680c50 /payloads/libpayload | |
| parent | 3db7653aabb98b02b9dbea0231fa68eacbbb5991 (diff) | |
| download | coreboot-baa3e70084bac00885667b20efde3e69901cda70.tar.xz | |
arm64: Align cache maintenance code with libpayload and ARM32
coreboot and libpayload currently use completely different code to
perform a full cache flush on ARM64, with even different function names.
The libpayload code is closely inspired by the ARM32 version, so for the
sake of overall consistency let's sync coreboot to that. Also align a
few other cache management details to work the same way as the
corresponding ARM32 parts (such as only flushing but not invalidating
the data cache after loading a new stage, which may have a small
performance benefit).
Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'payloads/libpayload')
| -rw-r--r-- | payloads/libpayload/arch/arm64/cache.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c index 0755c56731..2d42522588 100644 --- a/payloads/libpayload/arch/arm64/cache.c +++ b/payloads/libpayload/arch/arm64/cache.c @@ -119,7 +119,11 @@ void dcache_invalidate_by_mva(void const *addr, size_t len) void cache_sync_instructions(void) { - dcache_clean_all(); /* includes trailing DSB (in assembly) */ + uint32_t sctlr = raw_read_sctlr_current(); + if (sctlr & SCTLR_C) + dcache_clean_all(); /* includes trailing DSB (assembly) */ + else if (sctlr & SCTLR_I) + dcache_clean_invalidate_all(); icache_invalidate_all(); /* includes leading DSB and trailing ISB */ } |