diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-02-03 00:26:08 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-14 12:08:35 +0200 |
| commit | 0f58d0b941559c627153943891737cf8fb0a7430 (patch) | |
| tree | 8c7dbc6c3ca44ef42bc57bc9a4f10de1659ffb8a /payloads/nvramcui | |
| parent | a7023904e653a0ae869d53d9fad8a56baab2d94a (diff) | |
| download | coreboot-0f58d0b941559c627153943891737cf8fb0a7430.tar.xz | |
urara: Reduce MIPS PLL jitter
The current MIPS PLL is configured in such a way that there is
excessive jitter. Correct this by applying new PLL settings. The
resultant frequency is 546MHz instead of 550MHz.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board as part of the JTAG
loading script;
BRANCH=none
Change-Id: Ica1bfff29e01819b86cd2bb8b18d8adc9dfa3260
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0c04354b49b73d234492521d81b6600d487175b0
Original-Change-Id: I28b41b1e82dbdf9da21bf0ab74f9722cdad923f1
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245620
Original-Reviewed-by: James Hartley <james.hartley@imgtec.com>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: http://review.coreboot.org/9671
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'payloads/nvramcui')
0 files changed, 0 insertions, 0 deletions