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| author | Martin Roth <martinroth@chromium.org> | 2021-04-21 16:30:42 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-23 15:27:23 +0000 |
| commit | 3df27a66a11fa1832b7f09f04f86792568ff6edb (patch) | |
| tree | 0e46f1d8d94a129609f59831f98d95dec2321e5b /payloads | |
| parent | 7e241bff1883eba2b904cac06497670fd3440953 (diff) | |
| download | coreboot-3df27a66a11fa1832b7f09f04f86792568ff6edb.tar.xz | |
mb/google/guybrush: Update memory configuration
The next guybrush build uses 2 new LPDDR4X memory chips:
- Micro MT53E1G32D2NP-046 WT:B
- Hynix H9HCNNNBKMMLXR-NEE
The MT53E2G32D4NQ-046 WT:A chip has been added to the global LPDDR4X
list since the last time guybrush was updated, so that's brought into
the guybrush SPD directory as lp4x-spd-10.hex, but it's not used.
BUG=b:186027256
TEST=Build only
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia5efd548f8b9442fb3703518387175aba8933a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'payloads')
0 files changed, 0 insertions, 0 deletions