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| author | Raul E Rangel <rrangel@chromium.org> | 2021-05-07 14:25:09 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-09 18:09:05 +0000 |
| commit | 7502e10fdfe4085c5f7d03b0b29d0f7fb9b390fe (patch) | |
| tree | 1ad2caa0d9719b6c7f54603bc0a1ad378540ff32 /payloads | |
| parent | 1d1dbc4cfabf569b7d352dbcb5cee686fd5882d5 (diff) | |
| download | coreboot-7502e10fdfe4085c5f7d03b0b29d0f7fb9b390fe.tar.xz | |
soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT
This is loosely based off of picasso/pcie_gpp.c. This version uses the
acpigen_write_PRT_X methods to write the actual records. There are also
two functions, 1 for using the GNB, and one for using the FCH. The FCH
one is useful when the GNB IO-APIC has not been initialized.
BUG=b:184766519
TEST=Dump guybrush ACPI and verify it looks correct
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'payloads')
0 files changed, 0 insertions, 0 deletions