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author | Duncan Laurie <dlaurie@chromium.org> | 2013-08-09 09:06:41 -0700 |
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committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 12:02:34 +0100 |
commit | 249a03b080be30cccecf37354b19fc8b918be447 (patch) | |
tree | 0afc7033a85e5275db2dc8252539e2d60bae42bc /payloads | |
parent | 0b3cd36061d853a470f38415f71ca78bb3f9d331 (diff) | |
download | coreboot-249a03b080be30cccecf37354b19fc8b918be447.tar.xz |
lynxpoint: Add devicetree config option to force enable ASPM
The PCIe root port has ASPM settings/workarounds that are only applied
based on the value of an undocumented bit in PCI config register 0x32C.
If that bit is not set for some reason then the settings are not applied.
This devicetree config option will force the ASPM settings for each port
based on the bit map.
Change-Id: I40b08ca9a0ef52742609bac72fb821454a373799
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65314
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4453
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'payloads')
0 files changed, 0 insertions, 0 deletions