diff options
| author | David Hendricks <dhendrix@chromium.org> | 2015-01-27 09:27:54 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-17 09:27:42 +0200 |
| commit | f7da3d2a94dc996235b296569d1eff77842fe361 (patch) | |
| tree | bf21bdf8b5f8224e36dae362206ad48cd06c4714 /payloads | |
| parent | d73a8e5d3eb87722d9590f8c18bf3d1fbf0aaae9 (diff) | |
| download | coreboot-f7da3d2a94dc996235b296569d1eff77842fe361.tar.xz | |
libpayload: sync arch/arm/cache.c with coreboot
There was a recent patch by Deepa Dinamani applied to coreboot's
cache.c which fixed a bug that occurred when icache is on but dcache
is off ("arch: armv7: Fix cache sync instructions."). Although this
bug is not likely to be encountered by the time libpayload is run,
it's worth applying it to keep things in sync.
BUG=none
BRANCH=none
TEST=n/a since we have icache and dcache enabled on all ARM platforms
when libpayload is run.
Change-Id: I83d9f96acb702975585e5d47c90e2ddaca488f6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31f985b58ac9227684fbe27481129ba01fd3ab8a
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I4ab0d97ef3a97dcd0fa96e10273c3b32486e0b40
Original-Reviewed-on: https://chromium-review.googlesource.com/243276
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9737
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads')
| -rw-r--r-- | payloads/libpayload/arch/arm/cache.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/payloads/libpayload/arch/arm/cache.c b/payloads/libpayload/arch/arm/cache.c index 63715bc5a6..15cbf0a8d6 100644 --- a/payloads/libpayload/arch/arm/cache.c +++ b/payloads/libpayload/arch/arm/cache.c @@ -144,7 +144,15 @@ void dcache_mmu_enable(void) void cache_sync_instructions(void) { - dcache_clean_all(); /* includes trailing DSB (in assembly) */ + uint32_t sctlr; + + sctlr = read_sctlr(); + + if (sctlr & SCTLR_C) + dcache_clean_all(); + else if (sctlr & SCTLR_I) + dcache_clean_invalidate_all(); + iciallu(); /* includes BPIALLU (architecturally) */ dsb(); isb(); |