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| author | Furquan Shaikh <furquan@google.com> | 2015-03-31 22:50:17 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-22 08:56:17 +0200 |
| commit | fc45f0ba9750b8a7d27d7381a66b6204d66adb60 (patch) | |
| tree | 1c0b27e1b13a042a51d227211f57a8a92a22574d /payloads | |
| parent | c76926739507a0d20d3dde65192154c8982e4b90 (diff) | |
| download | coreboot-fc45f0ba9750b8a7d27d7381a66b6204d66adb60.tar.xz | |
libpayload: provide icache_invalidate_all() on ARM64
In order to not duplicate the instruction cache invalidation
sequence provide a common routine to perform the necessary
actions. Also, use it in the appropriate places.
BUG=chrome-os-partner:38231
BRANCH=None
TEST=Compiles successfully for smaug and boots kernel
Change-Id: I1d311dbc70bf225f35d60bb10d8d001065322b3a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ab015156713eb7531378edbd1d779522681d529
Original-Change-Id: I8da7002c56139f8f82503484bfd457a7ec20d083
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/263326
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9903
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads')
| -rw-r--r-- | payloads/libpayload/arch/arm64/cache.c | 4 | ||||
| -rw-r--r-- | payloads/libpayload/include/arm64/arch/cache.h | 11 |
2 files changed, 12 insertions, 3 deletions
diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c index 2ce1cc4a06..799e2d240c 100644 --- a/payloads/libpayload/arch/arm64/cache.c +++ b/payloads/libpayload/arch/arm64/cache.c @@ -120,7 +120,5 @@ void dcache_invalidate_by_mva(void const *addr, size_t len) void cache_sync_instructions(void) { dcache_clean_all(); /* includes trailing DSB (in assembly) */ - iciallu(); /* includes BPIALLU (architecturally) */ - dsb(); - isb(); + icache_invalidate_all(); /* includes leading DSB and trailing ISB */ } diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h index cfd3109559..757775886c 100644 --- a/payloads/libpayload/include/arm64/arch/cache.h +++ b/payloads/libpayload/include/arm64/arch/cache.h @@ -103,6 +103,17 @@ void cache_sync_instructions(void); /* tlb invalidate all */ void tlb_invalidate_all(void); +/* Invalidate all of the instruction cache for PE to PoU. */ +static inline void icache_invalidate_all(void) +{ + __asm__ __volatile__( + "dsb sy\n\t" + "ic iallu\n\t" + "dsb sy\n\t" + "isb\n\t" + : : : "memory"); +} + /* * Generalized setup/init functions */ |