diff options
| author | Naresh G Solanki <naresh.solanki@intel.com> | 2016-10-26 19:43:14 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-30 17:02:19 +0100 |
| commit | 335781ad53cd4988425e922cc24c966958484f0f (patch) | |
| tree | 14cd51d39a8de9c271cef7ea461d515ea5b351e2 /src/Kconfig | |
| parent | 500ba45b2c18a2742188d603808e2812fe6ed437 (diff) | |
| download | coreboot-335781ad53cd4988425e922cc24c966958484f0f.tar.xz | |
lib: Add library to handle SPD data in CBFS or DIMM
Add library to:
1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files.
2. runtime get spd data with spd index as input.
3. fetch spd over smbus using early smbus functions.
Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17434
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/Kconfig')
| -rw-r--r-- | src/Kconfig | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/Kconfig b/src/Kconfig index 610be5671c..77d13d1db8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -316,6 +316,31 @@ config GENERIC_GPIO_LIB implies configurability usually found on SoCs, particularly the ability to control internal pull resistors. +config GENERIC_SPD_BIN + bool + default n + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 2 + depends on GENERIC_SPD_BIN + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + depends on GENERIC_SPD_BIN + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + config BOARD_ID_AUTO bool default n |