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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-19 16:14:15 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-22 06:25:53 +0000 |
| commit | f8dc4bc0224f18a33fcf19e3d754ac96a383a863 (patch) | |
| tree | 058f1c05945113a64b8b22c88fde815efdaa6212 /src/Kconfig | |
| parent | 9bb16cd9c5b0fdf198f2b78c193d1a02f4f51338 (diff) | |
| download | coreboot-f8dc4bc0224f18a33fcf19e3d754ac96a383a863.tar.xz | |
arch/x86: Remove spinlocks inside CAR
This was only used with amdfam10h-15h, where cache
coherency between nodes was supposed to be guaranteed
with this code. We could want a cleaner and more generic
approach for this, possibly utilising .data sections.
Change-Id: I00da5c2b0570c26f2e3bb464274485cc2c08c8f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/Kconfig')
| -rw-r--r-- | src/Kconfig | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/Kconfig b/src/Kconfig index ba9ae86067..8df5323cf6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -527,22 +527,6 @@ config RESUME_PATH_SAME_AS_BOOT same path as a regular boot. e.g. an x86 system runs from the reset vector at 0xfffffff0 on both resume and warm/cold boot. -config HAVE_ROMSTAGE_CONSOLE_SPINLOCK - bool - default n - -config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK - bool - default n - help - This should be enabled on certain plaforms, such as the AMD - SR565x, that cannot handle concurrent CBFS accesses from - multiple APs during early startup. - -config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK - bool - default n - config NO_MONOTONIC_TIMER def_bool n |