diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-10-31 08:26:23 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-03-04 16:31:14 +0100 |
| commit | 7274800ea37edf41cb50e899d03baa02bdeecade (patch) | |
| tree | d49fb358ea2b46490bdf7007365ce4a3c0cb3cb7 /src/Kconfig | |
| parent | 0567c91b22e36eb07e7c7b8a67cbf6b41778db30 (diff) | |
| download | coreboot-7274800ea37edf41cb50e899d03baa02bdeecade.tar.xz | |
Add a generic register script handler
This is based on the RCBA configuration setup from haswell.
It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF.
I did not extend it to handle MSR yet but that would be another
potential register type.
There are a number of approaches to this kind of thing, but in the
end they have a lot of switch statements and a mass of #defines.
I'm not particularly set on any of the details so comments welcome.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=emerge-rambi chromeos-coreboot-rambi
Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175206
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4923
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/Kconfig')
| -rw-r--r-- | src/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/Kconfig b/src/Kconfig index 4040705f20..531a8c860b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1087,3 +1087,10 @@ config POWER_BUTTON_IS_OPTIONAL default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE) help Internal option that controls ENABLE_POWER_BUTTON visibility. + +config REG_SCRIPT + bool + default y if ARCH_X86 + default n + help + Internal option that controls whether we compile in register scripts. |