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| author | Subrata Banik <subrata.banik@intel.com> | 2020-02-09 19:13:52 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-02-11 02:34:32 +0000 |
| commit | 37bead6d26fc45f66e8032c50b3af619b246f1dc (patch) | |
| tree | 474223e1d691f81d20e2bbb14de2cce44e081061 /src/Kconfig | |
| parent | 8a3bc3be922766b6b9a34499dc2124f038b3f467 (diff) | |
| download | coreboot-37bead6d26fc45f66e8032c50b3af619b246f1dc.tar.xz | |
Kconfig: Guard CONFIGURABLE_RAMSTAGE
This patch guards CONFIGURABLE_RAMSTAGE symbol (which is default
enable for all x86 systems) with another Kconfig that can be selected
by platform that actually planning to use it.
TEST=CONFIG_CONFIGURABLE_RAMSTAGE is not enabled by default.
Change-Id: I2113445d507294df59fbc7fb1373793b47c6c31c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/Kconfig')
| -rw-r--r-- | src/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/Kconfig b/src/Kconfig index 3742c04675..4253ec7d52 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -354,9 +354,13 @@ config RAMPAYLOAD Skip PCI enumeration logic and only allocate BAR for fixed devices (bootable devices, TPM over GSPI). +config HAVE_CONFIGURABLE_RAMSTAGE + bool + config CONFIGURABLE_RAMSTAGE bool "Enable a configurable ramstage." default y if ARCH_X86 + depends on HAVE_CONFIGURABLE_RAMSTAGE help A configurable ramstage allows you to select which parts of the ramstage to run. Currently, we can only select a minimal PCI scanning step. |