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| author | Raul E Rangel <rrangel@chromium.org> | 2020-05-13 13:22:48 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:09:02 +0000 |
| commit | 5f52c0e91fc4ea545b6920157af7508b4a69a718 (patch) | |
| tree | 42d7ad5e6ec8ec252aeceee52877d95a2724e19b /src/acpi/pld.c | |
| parent | 8f694dd51f54c84a23251aeb175cb822da46cc9b (diff) | |
| download | coreboot-5f52c0e91fc4ea545b6920157af7508b4a69a718.tar.xz | |
soc/amd/picasso: Set VERSTAGE_ADDR for picasso
By default ROMSTAGE_ADDR and VERSTAGE_ADDR are set to 0x2000000. This
causes problems in a non-xip environment because when verstage loads
romstage, it overrides it's memory. So pick a different offset for
verstage.
BUG=b:147042464
TEST=Boot verstage on trembyle and see OS boot.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2464db6f3769bd23d250588b341d1c9e44f10d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41367
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/acpi/pld.c')
0 files changed, 0 insertions, 0 deletions