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authorMatt Papageorge <matthewpapa07@gmail.com>2021-03-25 11:22:47 -0500
committerFelix Held <felix-coreboot@felixheld.de>2021-04-07 22:48:43 +0000
commit5f5ca0c6f1b552d9f1bea58ff300926843d39547 (patch)
tree46024d38c007e215cb7a46b771292fb5320fcecb /src/acpi/sata.c
parentac57311575e3ca08504d5640c437e96aa8c12333 (diff)
downloadcoreboot-5f5ca0c6f1b552d9f1bea58ff300926843d39547.tar.xz
vc/amd/fsp/cezanne: update UPD headers
The UPD header files get generated as part of the FSP build process. For the initial Cezanne development we took the Picasso UPD data structures as a starting point. This patch replaces it with the first version of the Cezanne-specific UPD data structures that is present in version 12 of the internal work-in-progress FSP binary drops. The serial_port_stride UPD-M field is removed, since the information is already given by serial_port_use_mmio. The stride is 4 bytes for the MMIO UART case and 1 byte for the legacy I/O case. BUG=b:182524631 TEST=NVMe works on google/guybrush when the rest of the patch train is applied as well. Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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