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authorRaul E Rangel <rrangel@chromium.org>2021-04-19 15:58:25 -0600
committerRaul Rangel <rrangel@chromium.org>2021-04-21 22:27:55 +0000
commitc7048323f4a635ec854b2792a00ae47b1775d9f7 (patch)
tree63ea85da1bd8e70da54c88c2cda74d28e3f17577 /src/acpi
parenta89a4ea8ea04aaf369cd99f487f3537fe9e46702 (diff)
downloadcoreboot-c7048323f4a635ec854b2792a00ae47b1775d9f7.tar.xz
acpi: Add acpigen_write_LPI_package
Low Power Idle States defines additional information not present in the _CST. See ACPI Specification, Version 6.3 Section 8.4.4.3 _LPI. BUG=b:178728116, b:185787242 TEST=Boot guybrush and dump ACPI tables Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I4f5301b95ff8245facaf48e2fbd51cc82df2d8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/acpi')
-rw-r--r--src/acpi/acpigen.c72
1 files changed, 72 insertions, 0 deletions
diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
index 1131729da5..5c8c1b98c1 100644
--- a/src/acpi/acpigen.c
+++ b/src/acpi/acpigen.c
@@ -803,6 +803,78 @@ void acpigen_write_STA_ext(const char *namestring)
acpigen_pop_len();
}
+void acpigen_write_LPI_package(u64 level, const struct acpi_lpi_state *states, u16 nentries)
+{
+ /*
+ * Name (_LPI, Package (0x06) // _LPI: Low Power Idle States
+ * {
+ * 0x0000,
+ * 0x0000000000000000,
+ * 0x0003,
+ * Package (0x0A)
+ * {
+ * 0x00000002,
+ * 0x00000001,
+ * 0x00000001,
+ * 0x00000000,
+ * 0x00000000,
+ * 0x00000000,
+ * ResourceTemplate ()
+ * {
+ * Register (FFixedHW,
+ * 0x02, // Bit Width
+ * 0x02, // Bit Offset
+ * 0x0000000000000000, // Address
+ * ,)
+ * },
+ *
+ * ResourceTemplate ()
+ * {
+ * Register (SystemMemory,
+ * 0x00, // Bit Width
+ * 0x00, // Bit Offset
+ * 0x0000000000000000, // Address
+ * ,)
+ * },
+ *
+ * ResourceTemplate ()
+ * {
+ * Register (SystemMemory,
+ * 0x00, // Bit Width
+ * 0x00, // Bit Offset
+ * 0x0000000000000000, // Address
+ * ,)
+ * },
+ *
+ * "C1"
+ * },
+ * ...
+ * }
+ */
+
+ acpigen_write_name("_LPI");
+ acpigen_write_package(3 + nentries);
+ acpigen_write_word(0); /* Revision */
+ acpigen_write_qword(level);
+ acpigen_write_word(nentries);
+
+ for (size_t i = 0; i < nentries; i++, states++) {
+ acpigen_write_package(0xA);
+ acpigen_write_dword(states->min_residency_us);
+ acpigen_write_dword(states->worst_case_wakeup_latency_us);
+ acpigen_write_dword(states->flags);
+ acpigen_write_dword(states->arch_context_lost_flags);
+ acpigen_write_dword(states->residency_counter_frequency_hz);
+ acpigen_write_dword(states->enabled_parent_state);
+ acpigen_write_register_resource(&states->entry_method);
+ acpigen_write_register_resource(&states->residency_counter_register);
+ acpigen_write_register_resource(&states->usage_counter_register);
+ acpigen_write_string(states->state_name);
+ acpigen_pop_len();
+ }
+ acpigen_pop_len();
+}
+
/*
* Generates a func with max supported P-states.
*/