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authorLogan Carlson <logancarlson@google.com>2017-05-31 12:01:01 -0600
committerMartin Roth <martinroth@google.com>2017-07-21 20:40:27 +0000
commit50522254fbd063c7be6037a88e6712016a8586ab (patch)
treeec50055e421b99e45864de06987a5d8544cfb483 /src/arch/arm/armv7
parent80358a1f478713861a3e66874a1ffb7cf259bd7c (diff)
downloadcoreboot-50522254fbd063c7be6037a88e6712016a8586ab.tar.xz
arch/arm/armv7: Correct checkpatch errors
- Correct whitespace issues with files under arch/arm/armv7. - Fix comments and remove unnecessary line continuations in mmu.c Change-Id: I69d50030b07b1919555feca44967472922176a81 Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/arch/arm/armv7')
-rw-r--r--src/arch/arm/armv7/cache.c2
-rw-r--r--src/arch/arm/armv7/mmu.c10
-rw-r--r--src/arch/arm/armv7/thread.c2
3 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c
index eea514bd4b..ef3ad018fc 100644
--- a/src/arch/arm/armv7/cache.c
+++ b/src/arch/arm/armv7/cache.c
@@ -84,7 +84,7 @@ static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op)
dsb();
while ((void *)line < addr + len) {
- switch(op) {
+ switch (op) {
case OP_DCCIMVAC:
dccimvac(line);
break;
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 6b383ccfb0..957b4b6a7c 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -46,10 +46,10 @@
0ULL << 54 | /* XN. 0:Not restricted */ \
0ULL << 53 | /* PXN. 0:Not restricted */ \
1 << 10 | /* AF. 1:Accessed. This is to prevent access \
- * fault when accessed for the first time */ \
+ * fault when accessed for the first time */ \
0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \
0 << 5 | /* NS. 0:Output address is in Secure space */ \
- 0 << 1 | /* block/table. 0:block entry */ \
+ 0 << 1 | /* block/table. 0:block entry */ \
1 << 0 /* validity. 1:valid */ \
)
#define ATTR_PAGE (ATTR_BLOCK | 1 << 1)
@@ -280,12 +280,12 @@ void mmu_init(void)
table[0] = ATTR_UNUSED;
if (CONFIG_ARM_LPAE) {
- pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB);
+ pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB);
pte_t *pmd = ttb_buff;
int i;
printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
- ttb_buff);
+ ttb_buff);
ASSERT((read_mmfr0() & 0xf) >= 5);
/*
@@ -308,7 +308,7 @@ void mmu_init(void)
*/
for (i = 0; i < 4; i++) {
pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |
- ATTR_NEXTLEVEL;
+ ATTR_NEXTLEVEL;
pmd += BLOCK_SIZE / PAGE_SIZE;
}
diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c
index a3b1d0c13c..3b8d1af23e 100644
--- a/src/arch/arm/armv7/thread.c
+++ b/src/arch/arm/armv7/thread.c
@@ -39,7 +39,7 @@ static inline uintptr_t push_stack(uintptr_t cur_stack, uintptr_t value)
}
void arch_prepare_thread(struct thread *t,
- void asmlinkage (*thread_entry)(void *), void *arg)
+ void asmlinkage(*thread_entry)(void *), void *arg)
{
uintptr_t stack = t->stack_current;
int i;