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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-03 08:28:48 +0200
committerMartin Roth <martinroth@google.com>2016-09-12 20:05:30 +0200
commit6b72787d270077969869e9b17b88a63539f172b4 (patch)
treef203c91e18b7a1320783f4b1e478c335d6696f3e /src/arch/arm/armv7
parentc7702536ed7b9d80058e2d41c396828c3a1ac20b (diff)
downloadcoreboot-6b72787d270077969869e9b17b88a63539f172b4.tar.xz
src/arch: Improve code formatting
Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16434 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
Diffstat (limited to 'src/arch/arm/armv7')
-rw-r--r--src/arch/arm/armv7/mmu.c90
-rw-r--r--src/arch/arm/armv7/thread.c4
2 files changed, 47 insertions, 47 deletions
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index b1c1aac0c0..6c085e920e 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -280,53 +280,53 @@ void mmu_init(void)
for (; (pte_t *)_ettb_subtables - table > 0; table += SUBTABLE_PTES)
table[0] = ATTR_UNUSED;
- if (CONFIG_ARM_LPAE) {
- pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB);
- pte_t *pmd = ttb_buff;
- int i;
+ if (CONFIG_ARM_LPAE) {
+ pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB);
+ pte_t *pmd = ttb_buff;
+ int i;
- printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
+ printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
ttb_buff);
- ASSERT((read_mmfr0() & 0xf) >= 5);
-
- /*
- * Set MAIR
- * See B4.1.104 of ARMv7 Architecture Reference Manual
- */
- write_mair0(
- 0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered,
- * Non-Cacheable */
- 0xaa << (MAIR_INDX_WT*8) | /* Write-Thru,
- * Read-Allocate */
- 0xff << (MAIR_INDX_WB*8) /* Write-Back,
- * Read/Write-Allocate */
- );
-
- /*
- * Set up L1 table
- * Once set here, L1 table won't be modified by coreboot.
- * See B3.6.1 of ARMv7 Architecture Reference Manual
- */
- for (i = 0; i < 4; i++) {
- pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |
- ATTR_NEXTLEVEL;
- pmd += BLOCK_SIZE / PAGE_SIZE;
- }
-
- /*
- * Set TTBR0
- */
- write_ttbr0((uintptr_t)pgd_buff);
- } else {
- printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);
-
- /*
- * Translation table base 0 address is in bits 31:14-N, where N
- * is given by bits 2:0 in TTBCR (which we set to 0). All lower
- * bits in this register should be zero for coreboot.
- */
- write_ttbr0((uintptr_t)ttb_buff);
- }
+ ASSERT((read_mmfr0() & 0xf) >= 5);
+
+ /*
+ * Set MAIR
+ * See B4.1.104 of ARMv7 Architecture Reference Manual
+ */
+ write_mair0(
+ 0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered,
+ * Non-Cacheable */
+ 0xaa << (MAIR_INDX_WT*8) | /* Write-Thru,
+ * Read-Allocate */
+ 0xff << (MAIR_INDX_WB*8) /* Write-Back,
+ * Read/Write-Allocate */
+ );
+
+ /*
+ * Set up L1 table
+ * Once set here, L1 table won't be modified by coreboot.
+ * See B3.6.1 of ARMv7 Architecture Reference Manual
+ */
+ for (i = 0; i < 4; i++) {
+ pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |
+ ATTR_NEXTLEVEL;
+ pmd += BLOCK_SIZE / PAGE_SIZE;
+ }
+
+ /*
+ * Set TTBR0
+ */
+ write_ttbr0((uintptr_t)pgd_buff);
+ } else {
+ printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);
+
+ /*
+ * Translation table base 0 address is in bits 31:14-N, where N
+ * is given by bits 2:0 in TTBCR (which we set to 0). All lower
+ * bits in this register should be zero for coreboot.
+ */
+ write_ttbr0((uintptr_t)ttb_buff);
+ }
/*
* Set TTBCR
diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c
index 53ca2b3054..a3b1d0c13c 100644
--- a/src/arch/arm/armv7/thread.c
+++ b/src/arch/arm/armv7/thread.c
@@ -55,7 +55,7 @@ void arch_prepare_thread(struct thread *t,
* hunting for (e.g.) misaligned stacks or other such
* weirdness. The -1 is because we already pushed lr.
*/
- for (i = 0; i < sizeof(struct pushed_regs)/sizeof(u32)-1; i++)
+ for (i = 0; i < sizeof(struct pushed_regs) / sizeof(u32) - 1; i++)
stack = push_stack(stack, poison++);
t->stack_current = stack;
@@ -103,7 +103,7 @@ switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack)
* | R4 | <-- sp + 0x00
* +------------+
*/
- asm volatile (
+ asm volatile (
/* save context. */
"push {r4-r11,lr}\n\t"
/* Save the current stack */