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| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/arch/arm/include | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/arm/include')
| -rw-r--r-- | src/arch/arm/include/arch/memlayout.h | 8 | ||||
| -rw-r--r-- | src/arch/arm/include/armv7/arch/cache.h | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h index f7837b68c8..4ba2bf8cf2 100644 --- a/src/arch/arm/include/arch/memlayout.h +++ b/src/arch/arm/include/arch/memlayout.h @@ -18,16 +18,16 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -#define SUPERPAGE_SIZE ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M) +#define SUPERPAGE_SIZE ((1 + CONFIG(ARM_LPAE)) * 1M) #define TTB(addr, size) \ REGION(ttb, addr, size, 16K) \ - _ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \ + _ = ASSERT(size >= 16K + CONFIG(ARM_LPAE) * 32, \ "TTB must be 16K (+ 32 for LPAE)!"); #define TTB_SUBTABLES(addr, size) \ - REGION(ttb_subtables, addr, size, IS_ENABLED(CONFIG_ARM_LPAE)*3K + 1K) \ - _ = ASSERT(size % (1K + 3K * IS_ENABLED(CONFIG_ARM_LPAE)) == 0, \ + REGION(ttb_subtables, addr, size, CONFIG(ARM_LPAE)*3K + 1K) \ + _ = ASSERT(size % (1K + 3K * CONFIG(ARM_LPAE)) == 0, \ "TTB subtable region must be evenly divisible by table size!"); /* ARM stacks need 8-byte alignment and stay in one place through ramstage. */ diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index 9a8021761e..b2b6a33333 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -134,7 +134,7 @@ static inline void write_mair0(uint32_t val) /* write translation table base register 0 (TTBR0) */ static inline void write_ttbr0(uint32_t val) { - if (IS_ENABLED(CONFIG_ARM_LPAE)) + if (CONFIG(ARM_LPAE)) asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : : [val] "r" (val), [zero] "r" (0)); else |