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authorElyes HAOUAS <ehaouas@noos.fr>2018-06-29 21:41:41 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-07-02 07:39:51 +0000
commite3e3f4f4ed4fee2f739806a81a7323fefe63e96d (patch)
tree56fe3cdaa378ed0e6719fb0b46ca6ec2fa73c110 /src/arch/arm/include
parent21b71ce66b89f7bff7959027d971e9a7786bf219 (diff)
downloadcoreboot-e3e3f4f4ed4fee2f739806a81a7323fefe63e96d.tar.xz
src: Get rid of unneeded whitespace
Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/arm/include')
-rw-r--r--src/arch/arm/include/armv7/arch/cache.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index dd271c5bce..9a8021761e 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -48,8 +48,8 @@
#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
#define SCTLR_Z (1 << 11) /* Branch prediction enable */
#define SCTLR_I (1 << 12) /* Instruction cache enable */
-#define SCTLR_V (1 << 13) /* Low/high exception vectors */
-#define SCTLR_RR (1 << 14) /* Round Robin select */
+#define SCTLR_V (1 << 13) /* Low/high exception vectors */
+#define SCTLR_RR (1 << 14) /* Round Robin select */
/* Bits 16:15 are reserved */
#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
/* Bit 18 is reserved */