diff options
| author | Joseph Lo <josephl@nvidia.com> | 2015-04-14 16:03:58 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-27 07:44:49 +0200 |
| commit | c4301f79691995dfedb56cb3e20adea3ecd8f596 (patch) | |
| tree | 798d7561c82ce946ebca4e81028b8d178440d5bc /src/arch/arm64/armv8/cache.c | |
| parent | 53a2f6078ac28738b6b52148eb8d90b2fc4132b5 (diff) | |
| download | coreboot-c4301f79691995dfedb56cb3e20adea3ecd8f596.tar.xz | |
arm64: introduce data cache ops by set/way to the level specified
This patchs introduces level specific data cache maintenance operations
to cache_helpers.S. It's derived form ARM trusted firmware repository.
Please reference here.
https://github.com/ARM-software/arm-trusted-firmware/blob/master/
lib/aarch64/cache_helpers.S
BRANCH=none
BUG=none
TEST=boot on smaug/foster
Change-Id: Ib58a6d6f95eb51ce5d80749ff51d9d389b0d1343
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b3d1a16bd0089740f1f2257146c771783beece82
Original-Change-Id: Ifcd1dbcd868331107d0d47af73545a3a159fdff6
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/265826
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9979
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/arch/arm64/armv8/cache.c')
| -rw-r--r-- | src/arch/arm64/armv8/cache.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index d568f261ed..db9b3882bc 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -34,6 +34,7 @@ #include <stdint.h> #include <arch/cache.h> +#include <arch/cache_helpers.h> #include <arch/lib_helpers.h> void tlb_invalidate_all(void) @@ -126,7 +127,7 @@ void dcache_mmu_disable(void) { uint32_t sctlr; - flush_dcache_all(); + flush_dcache_all(DCCISW); sctlr = raw_read_sctlr_current(); sctlr &= ~(SCTLR_C | SCTLR_M); raw_write_sctlr_current(sctlr); @@ -143,6 +144,6 @@ void dcache_mmu_enable(void) void cache_sync_instructions(void) { - flush_dcache_all(); /* includes trailing DSB (in assembly) */ + flush_dcache_all(DCCISW); /* includes trailing DSB (in assembly) */ icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */ } |