arm64: Drop checks for current exception level, hardcode EL3 assumption

When we first created the arm64 port, we weren't quite sure whether
coreboot would always run in EL3 on all platforms. The AArch64 A.R.M.
technically considers this exception level optional, but in practice all
SoCs seem to support it. We have since accumulated a lot of code that
already hardcodes an implicit or explicit assumption of executing in EL3
somewhere, so coreboot wouldn't work on a system that tries to enter it
in EL1/2 right now anyway.

However, some of our low level support libraries (in particular those
for accessing architectural registers) still have provisions for
running at different exception levels built-in, and often use switch
statements over the current exception level to decide which register to
access. This includes an unnecessarily large amount of code for what
should be single-instruction operations and precludes further
optimization via inlining.

This patch removes any remaining code that dynamically depends on the
current exception level and makes the assumption that coreboot executes
at EL3 official. If this ever needs to change for a future platform, it
would probably be cleaner to set the expected exception level in a
Kconfig rather than always probing it at runtime.

Change-Id: I1a9fb9b4227bd15a013080d1c7eabd48515fdb67
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

6 files changed, 6 insertions, 380 deletions

diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c
index 59d56b2902..2e63db3bbb 100644
--- a/src/arch/arm64/armv8/cache.c
+++ b/src/arch/arm64/armv8/cache.c
@@ -40,7 +40,7 @@
 void tlb_invalidate_all(void)
 {
 	 /* TLBIALL includes dTLB and iTLB on systems that have them. */
-	tlbiall_current();
+	tlbiall_el3();
 	dsb();
 	isb();
 }
@@ -124,7 +124,7 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
  */
 void arch_segment_loaded(uintptr_t start, size_t size, int flags)
 {
-	uint32_t sctlr = raw_read_sctlr_current();
+	uint32_t sctlr = raw_read_sctlr_el3();
 	if (sctlr & SCTLR_C)
 		dcache_clean_by_mva((void *)start, size);
 	else if (sctlr & SCTLR_I)
diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c
index c5cbbfea3b..924c344e13 100644
--- a/src/arch/arm64/armv8/exception.c
+++ b/src/arch/arm64/armv8/exception.c
@@ -79,9 +79,9 @@ static void print_regs(struct exc_state *exc_state)
 	struct regs *regs = &exc_state->regs;
 
 	printk(BIOS_DEBUG, "ELR = 0x%016llx         ESR = 0x%08x\n",
-	       elx->elr, raw_read_esr_current());
+	       elx->elr, raw_read_esr_el3());
 	printk(BIOS_DEBUG, "FAR = 0x%016llx        SPSR = 0x%08x\n",
-	       raw_read_far_current(), raw_read_spsr_current());
+	       raw_read_far_el3(), raw_read_spsr_el3());
 	for (i = 0; i < 30; i += 2) {
 		printk(BIOS_DEBUG,
 		       "X%02d = 0x%016llx         X%02d = 0x%016llx\n",
@@ -188,7 +188,7 @@ static int test_exception_handler(struct exc_state *state, uint64_t vector_id)
 {
 	/* Update instruction pointer to next instrution. */
 	state->elx.elr += sizeof(uint32_t);
-	raw_write_elr_current(state->elx.elr);
+	raw_write_elr_el3(state->elx.elr);
 	return EXC_RET_HANDLED;
 }
 
diff --git a/src/arch/arm64/armv8/lib/pstate.c b/src/arch/arm64/armv8/lib/pstate.c
index e068031bd2..631974f6e0 100644
--- a/src/arch/arm64/armv8/lib/pstate.c
+++ b/src/arch/arm64/armv8/lib/pstate.c
@@ -32,12 +32,6 @@ uint32_t raw_read_current_el(void)
 	return current_el;
 }
 
-uint32_t get_current_el(void)
-{
-	uint32_t current_el = raw_read_current_el();
-	return ((current_el >> CURRENT_EL_SHIFT) & CURRENT_EL_MASK);
-}
-
 /* DAIF */
 uint32_t raw_read_daif(void)
 {
@@ -164,28 +158,6 @@ void raw_write_elr_el3(uint64_t elr_el3)
 	__asm__ __volatile__("msr ELR_EL3, %0\n\t" : : "r" (elr_el3) : "memory");
 }
 
-uint64_t raw_read_elr_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_elr(el);
-}
-
-void raw_write_elr_current(uint64_t elr)
-{
-	uint32_t el = get_current_el();
-	raw_write_elr(elr, el);
-}
-
-uint64_t raw_read_elr(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_elr, elr, uint64_t, el);
-}
-
-void raw_write_elr(uint64_t elr, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_elr, elr, el);
-}
-
 /* FPCR */
 uint32_t raw_read_fpcr(void)
 {
@@ -320,16 +292,6 @@ void raw_write_sp_el3(uint64_t sp_el3)
 		raw_write_spsel(spsel);
 }
 
-uint64_t raw_read_sp_elx(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_sp, sp, uint64_t, el);
-}
-
-void raw_write_sp_elx(uint64_t sp_elx, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_sp, sp_elx, el);
-}
-
 /* SPSR */
 uint32_t raw_read_spsr_abt(void)
 {
@@ -387,28 +349,6 @@ void raw_write_spsr_el3(uint32_t spsr_el3)
 	__asm__ __volatile__("msr SPSR_EL3, %0\n\t" : : "r" ((uint64_t)spsr_el3) : "memory");
 }
 
-uint32_t raw_read_spsr_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_spsr(el);
-}
-
-void raw_write_spsr_current(uint32_t spsr)
-{
-	uint32_t el = get_current_el();
-	raw_write_spsr(spsr, el);
-}
-
-uint32_t raw_read_spsr(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_spsr, spsr, uint32_t, el);
-}
-
-void raw_write_spsr(uint32_t spsr, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_spsr, spsr, el);
-}
-
 uint32_t raw_read_spsr_fiq(void)
 {
 	uint64_t spsr_fiq;
diff --git a/src/arch/arm64/armv8/lib/sysctrl.c b/src/arch/arm64/armv8/lib/sysctrl.c
index ef3b455b65..3e73c30173 100644
--- a/src/arch/arm64/armv8/lib/sysctrl.c
+++ b/src/arch/arm64/armv8/lib/sysctrl.c
@@ -65,28 +65,6 @@ void raw_write_actlr_el3(uint32_t actlr_el3)
 	__asm__ __volatile__("msr ACTLR_EL3, %0\n\t" : : "r" ((uint64_t)actlr_el3) : "memory");
 }
 
-uint32_t raw_read_actlr_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_actlr(el);
-}
-
-void raw_write_actlr_current(uint32_t actlr)
-{
-	uint32_t el = get_current_el();
-	raw_write_actlr(actlr, el);
-}
-
-uint32_t raw_read_actlr(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_actlr, actlr, uint32_t, el);
-}
-
-void raw_write_actlr(uint32_t actlr, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_actlr, actlr, el);
-}
-
 /* AFSR0 */
 uint32_t raw_read_afsr0_el1(void)
 {
@@ -130,28 +108,6 @@ void raw_write_afsr0_el3(uint32_t afsr0_el3)
 	__asm__ __volatile__("msr AFSR0_EL3, %0\n\t" : : "r" ((uint64_t)afsr0_el3) : "memory");
 }
 
-uint32_t raw_read_afsr0_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_afsr0(el);
-}
-
-void raw_write_afsr0_current(uint32_t afsr0)
-{
-	uint32_t el = get_current_el();
-	raw_write_afsr0(afsr0, el);
-}
-
-uint32_t raw_read_afsr0(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_afsr0, afsr0, uint32_t, el);
-}
-
-void raw_write_afsr0(uint32_t afsr0, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_afsr0, afsr0, el);
-}
-
 /* AFSR1 */
 uint32_t raw_read_afsr1_el1(void)
 {
@@ -195,28 +151,6 @@ void raw_write_afsr1_el3(uint32_t afsr1_el3)
 	__asm__ __volatile__("msr AFSR1_EL3, %0\n\t" : : "r" ((uint64_t)afsr1_el3) : "memory");
 }
 
-uint32_t raw_read_afsr1_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_afsr1(el);
-}
-
-void raw_write_afsr1_current(uint32_t afsr1)
-{
-	uint32_t el = get_current_el();
-	raw_write_afsr1(afsr1, el);
-}
-
-uint32_t raw_read_afsr1(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_afsr1, afsr1, uint32_t, el);
-}
-
-void raw_write_afsr1(uint32_t afsr1, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_afsr1, afsr1, el);
-}
-
 /* AIDR */
 uint32_t raw_read_aidr_el1(void)
 {
@@ -270,28 +204,6 @@ void raw_write_amair_el3(uint64_t amair_el3)
 	__asm__ __volatile__("msr AMAIR_EL3, %0\n\t" : : "r" (amair_el3) : "memory");
 }
 
-uint64_t raw_read_amair_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_amair(el);
-}
-
-void raw_write_amair_current(uint64_t amair)
-{
-	uint32_t el = get_current_el();
-	raw_write_amair(amair, el);
-}
-
-uint64_t raw_read_amair(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_amair, amair, uint64_t, el);
-}
-
-void raw_write_amair(uint64_t amair, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_amair, amair, el);
-}
-
 /* CCSIDR */
 uint32_t raw_read_ccsidr_el1(void)
 {
@@ -424,28 +336,6 @@ void raw_write_esr_el3(uint32_t esr_el3)
 	__asm__ __volatile__("msr ESR_EL3, %0\n\t" : : "r" ((uint64_t)esr_el3) : "memory");
 }
 
-uint32_t raw_read_esr_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_esr(el);
-}
-
-void raw_write_esr_current(uint32_t esr)
-{
-	uint32_t el = get_current_el();
-	raw_write_esr(esr, el);
-}
-
-uint32_t raw_read_esr(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_esr, esr, uint32_t, el);
-}
-
-void raw_write_esr(uint32_t esr, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_esr, esr, el);
-}
-
 /* FAR */
 uint64_t raw_read_far_el1(void)
 {
@@ -489,28 +379,6 @@ void raw_write_far_el3(uint64_t far_el3)
 	__asm__ __volatile__("msr FAR_EL3, %0\n\t" : : "r" (far_el3) : "memory");
 }
 
-uint64_t raw_read_far_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_far(el);
-}
-
-void raw_write_far_current(uint64_t far)
-{
-	uint32_t el = get_current_el();
-	raw_write_far(far, el);
-}
-
-uint64_t raw_read_far(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_far, far, uint64_t, el);
-}
-
-void raw_write_far(uint64_t far, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_far, far, el);
-}
-
 /* HCR */
 uint64_t raw_read_hcr_el2(void)
 {
@@ -579,28 +447,6 @@ void raw_write_mair_el3(uint64_t mair_el3)
 	__asm__ __volatile__("msr MAIR_EL3, %0\n\t" : : "r" (mair_el3) : "memory");
 }
 
-uint64_t raw_read_mair_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_mair(el);
-}
-
-void raw_write_mair_current(uint64_t mair)
-{
-	uint32_t el = get_current_el();
-	raw_write_mair(mair, el);
-}
-
-uint64_t raw_read_mair(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_mair, mair, uint64_t, el);
-}
-
-void raw_write_mair(uint64_t mair, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_mair, mair, el);
-}
-
 /* MIDR */
 uint32_t raw_read_midr_el1(void)
 {
@@ -664,28 +510,6 @@ void raw_write_rmr_el3(uint32_t rmr_el3)
 	__asm__ __volatile__("msr RMR_EL3, %0\n\t" : : "r" ((uint64_t)rmr_el3) : "memory");
 }
 
-uint32_t raw_read_rmr_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_rmr(el);
-}
-
-void raw_write_rmr_current(uint32_t rmr)
-{
-	uint32_t el = get_current_el();
-	raw_write_rmr(rmr, el);
-}
-
-uint32_t raw_read_rmr(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_rmr, rmr, uint32_t, el);
-}
-
-void raw_write_rmr(uint32_t rmr, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_rmr, rmr, el);
-}
-
 /* RVBAR */
 uint64_t raw_read_rvbar_el1(void)
 {
@@ -729,28 +553,6 @@ void raw_write_rvbar_el3(uint64_t rvbar_el3)
 	__asm__ __volatile__("msr RVBAR_EL3, %0\n\t" : : "r" (rvbar_el3) : "memory");
 }
 
-uint64_t raw_read_rvbar_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_rvbar(el);
-}
-
-void raw_write_rvbar_current(uint64_t rvbar)
-{
-	uint32_t el = get_current_el();
-	raw_write_rvbar(rvbar, el);
-}
-
-uint64_t raw_read_rvbar(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_rvbar, rvbar, uint64_t, el);
-}
-
-void raw_write_rvbar(uint64_t rvbar, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_rvbar, rvbar, el);
-}
-
 /* Scr */
 uint32_t raw_read_scr_el3(void)
 {
@@ -809,28 +611,6 @@ void raw_write_sctlr_el3(uint32_t sctlr_el3)
 	__asm__ __volatile__("msr SCTLR_EL3, %0\n\t" : : "r" ((uint64_t)sctlr_el3) : "memory");
 }
 
-uint32_t raw_read_sctlr_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_sctlr(el);
-}
-
-void raw_write_sctlr_current(uint32_t sctlr)
-{
-	uint32_t el = get_current_el();
-	raw_write_sctlr(sctlr, el);
-}
-
-uint32_t raw_read_sctlr(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_sctlr, sctlr, uint32_t, el);
-}
-
-void raw_write_sctlr(uint32_t sctlr, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_sctlr, sctlr, el);
-}
-
 /* TCR */
 uint64_t raw_read_tcr_el1(void)
 {
@@ -874,34 +654,6 @@ void raw_write_tcr_el3(uint32_t tcr_el3)
 	__asm__ __volatile__("msr TCR_EL3, %0\n\t" : : "r" ((uint64_t)tcr_el3) : "memory");
 }
 
-
-/*
- * IMPORTANT: TCR_EL1 is 64-bit whereas TCR_EL2 and TCR_EL3 are 32-bit. Thus,
- * 64-bit is used to read/write for tcr_current. tcr_el2 and tcr_el3 handle them
- * with appropriate 32-bit types.
- */
-uint64_t raw_read_tcr_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_tcr(el);
-}
-
-void raw_write_tcr_current(uint64_t tcr)
-{
-	uint32_t el = get_current_el();
-	raw_write_tcr(tcr, el);
-}
-
-uint64_t raw_read_tcr(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_tcr, tcr, uint64_t, el);
-}
-
-void raw_write_tcr(uint64_t tcr, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_tcr, tcr, el);
-}
-
 /* TTBR0 */
 uint64_t raw_read_ttbr0_el1(void)
 {
@@ -945,28 +697,6 @@ void raw_write_ttbr0_el3(uint64_t ttbr0_el3)
 	__asm__ __volatile__("msr TTBR0_EL3, %0\n\t" : : "r" (ttbr0_el3) : "memory");
 }
 
-uint64_t raw_read_ttbr0_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_ttbr0(el);
-}
-
-void raw_write_ttbr0_current(uint64_t ttbr0)
-{
-	uint32_t el = get_current_el();
-	raw_write_ttbr0(ttbr0, el);
-}
-
-uint64_t raw_read_ttbr0(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_ttbr0, ttbr0, uint64_t, el);
-}
-
-void raw_write_ttbr0(uint64_t ttbr0, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_ttbr0, ttbr0, el);
-}
-
 /* TTBR1 */
 uint64_t raw_read_ttbr1_el1(void)
 {
@@ -1025,28 +755,6 @@ void raw_write_vbar_el3(uint64_t vbar_el3)
 	__asm__ __volatile__("msr VBAR_EL3, %0\n\t" : : "r" (vbar_el3) : "memory");
 }
 
-uint64_t raw_read_vbar_current(void)
-{
-	uint32_t el = get_current_el();
-	return raw_read_vbar(el);
-}
-
-void raw_write_vbar_current(uint64_t vbar)
-{
-	uint32_t el = get_current_el();
-	raw_write_vbar(vbar, el);
-}
-
-uint64_t raw_read_vbar(uint32_t el)
-{
-	SWITCH_CASE_READ(raw_read_vbar, vbar, uint64_t, el);
-}
-
-void raw_write_vbar(uint64_t vbar, uint32_t el)
-{
-	SWITCH_CASE_WRITE(raw_write_vbar, vbar, el);
-}
-
 uint32_t raw_read_cntfrq_el0(void)
 {
 	uint64_t cntfrq_el0;
diff --git a/src/arch/arm64/armv8/lib/tlb.c b/src/arch/arm64/armv8/lib/tlb.c
index d04afcf4ad..b40fb8f135 100644
--- a/src/arch/arm64/armv8/lib/tlb.c
+++ b/src/arch/arm64/armv8/lib/tlb.c
@@ -37,17 +37,6 @@ void tlbiall_el3(void)
 	__asm__ __volatile__("tlbi alle3\n\t" : : : "memory");
 }
 
-void tlbiall_current(void)
-{
-	uint32_t el = get_current_el();
-	tlbiall(el);
-}
-
-void tlbiall(uint32_t el)
-{
-	SWITCH_CASE_TLBI(tlbiall, el);
-}
-
 /* TLBIALLIS */
 void tlbiallis_el1(void)
 {
@@ -64,17 +53,6 @@ void tlbiallis_el3(void)
 	__asm__ __volatile__("tlbi alle3is\n\t" : : : "memory");
 }
 
-void tlbiallis_current(void)
-{
-	uint32_t el = get_current_el();
-	tlbiallis(el);
-}
-
-void tlbiallis(uint32_t el)
-{
-	SWITCH_CASE_TLBI(tlbiallis, el);
-}
-
 /* TLBIVAA */
 void tlbivaa_el1(uint64_t va)
 {
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 606a9b30ad..742f097d0d 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -242,7 +242,7 @@ void mmu_config_range(void *start, size_t size, uint64_t tag)
 
 	/* ARMv8 MMUs snoop L1 data cache, no need to flush it. */
 	dsb();
-	tlbiall_current();
+	tlbiall_el3();
 	dsb();
 	isb();
 }