coreboot arm64: Add library for system access

Add support for library functions required to access different system registers:
1) PSTATE and special purpose registers
2) System control registers
3) Cache-related registers
4) TLB maintenance registers
5) Misc barrier related functions

BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203490
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb)

armv8: GPL license armv8 lib

BUG=None
BRANCH=None
TEST=Compiles successfully.

Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250950
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e)

Get the library and the GPL license in a single commit.

Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d
Reviewed-on: http://review.coreboot.org/8465
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

3 files changed, 297 insertions, 175 deletions

diff --git a/src/arch/arm64/include/armv8/arch/arch_io.h b/src/arch/arm64/include/armv8/arch/arch_io.h
index 56ed86dbf9..2876c8b78c 100644
--- a/src/arch/arm64/include/armv8/arch/arch_io.h
+++ b/src/arch/arm64/include/armv8/arch/arch_io.h
@@ -23,8 +23,8 @@
 #ifndef __ASM_ARM64_ARCH_IO_H
 #define __ASM_ARM64_ARCH_IO_H
 
-#include <arch/cache.h>		/* for dmb() */
 #include <stdint.h>
+#include <arch/lib_helpers.h>
 
 static inline uint8_t read8(const void *addr)
 {
diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h
index 325b85757b..977edbaeff 100644
--- a/src/arch/arm64/include/armv8/arch/cache.h
+++ b/src/arch/arm64/include/armv8/arch/cache.h
@@ -57,180 +57,6 @@
 #define SCTLR_EL1_E0E	(1 << 24)	/* Exception endianness at EL0	*/
 #define SCTLR_EL1_UCI	(1 << 26)	/* EL0 access to cache instructions */
 
-/*
- * Utility macro to choose an instruction according to the exception
- * level (EL) passed, which number is concatenated between insa and insb parts
- */
-#define SWITCH_EL(insa, insb, el) if (el == 1) asm volatile(insa "1" insb); \
-	else if (el == 2) asm volatile (insa "2" insb); \
-	else asm volatile (insa "3" insb)
-
-/* get current exception level (EL1-EL3) */
-static inline uint32_t current_el(void)
-{
-	uint32_t el;
-	asm volatile ("mrs %0, CurrentEL" : "=r" (el));
-	return el >> 2;
-}
-
-/*
- * Sync primitives
- */
-
-/* data memory barrier */
-static inline void dmb(void)
-{
-	asm volatile ("dmb sy" : : : "memory");
-}
-
-/* data sync barrier */
-static inline void dsb(void)
-{
-	asm volatile ("dsb sy" : : : "memory");
-}
-
-/* instruction sync barrier */
-static inline void isb(void)
-{
-	asm volatile ("isb sy" : : : "memory");
-}
-
-/*
- * Low-level TLB maintenance operations
- */
-
-/* invalidate entire unified TLB */
-static inline void tlbiall(uint32_t el)
-{
-	SWITCH_EL("tlbi alle", : : : "memory", el);
-}
-
-/* invalidate unified TLB by VA, all ASID (EL1) */
-static inline void tlbivaa(uint64_t va)
-{
-	asm volatile("tlbi vaae1, %0" : : "r" (va) : "memory");
-}
-
-/* write translation table base register 0 (TTBR0_ELx) */
-static inline void write_ttbr0(uint64_t val, uint32_t el)
-{
-	SWITCH_EL("msr ttbr0_el", ", %0" : : "r" (val) : "memory", el);
-}
-
-/* read translation control register (TCR_ELx) */
-static inline uint64_t read_tcr(uint32_t el)
-{
-	uint64_t val = 0;
-	SWITCH_EL("mrs %0, tcr_el", : "=r" (val), el);
-	return val;
-}
-
-/* write translation control register (TCR_ELx) */
-static inline void write_tcr(uint64_t val, uint32_t el)
-{
-	SWITCH_EL("msr tcr_el", ", %0" : : "r" (val) : "memory", el);
-}
-
-/*
- * Low-level cache maintenance operations
- */
-
-/* data cache clean and invalidate by VA to PoC */
-static inline void dccivac(uint64_t va)
-{
-	asm volatile ("dc civac, %0" : : "r" (va) : "memory");
-}
-
-/* data cache clean and invalidate by set/way */
-static inline void dccisw(uint64_t val)
-{
-	asm volatile ("dc cisw, %0" : : "r" (val) : "memory");
-}
-
-/* data cache clean by VA to PoC */
-static inline void dccvac(uint64_t va)
-{
-	asm volatile ("dc cvac, %0" : : "r" (va) : "memory");
-}
-
-/* data cache clean by set/way */
-static inline void dccsw(uint64_t val)
-{
-	asm volatile ("dc csw, %0" : : "r" (val) : "memory");
-}
-
-/* data cache invalidate by VA to PoC */
-static inline void dcivac(uint64_t va)
-{
-	asm volatile ("dc ivac, %0" : : "r" (va) : "memory");
-}
-
-/* data cache invalidate by set/way */
-static inline void dcisw(uint64_t val)
-{
-	asm volatile ("dc isw, %0" : : "r" (val) : "memory");
-}
-
-/* instruction cache invalidate all */
-static inline void iciallu(void)
-{
-	asm volatile ("ic iallu" : : : "memory");
-}
-
-/*
- * Cache registers functions
- */
-
-/* read cache level ID register (CLIDR_EL1) */
-static inline uint32_t read_clidr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrs %0, clidr_el1" : "=r" (val));
-	return val;
-}
-
-/* read cache size ID register register (CCSIDR_EL1) */
-static inline uint32_t read_ccsidr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrs %0, ccsidr_el1" : "=r" (val));
-	return val;
-}
-
-/* read cache size selection register (CSSELR_EL1) */
-static inline uint32_t read_csselr(void)
-{
-	uint32_t val = 0;
-	asm volatile ("mrs %0, csselr_el1" : "=r" (val));
-	return val;
-}
-
-/* write to cache size selection register (CSSELR_EL1) */
-static inline void write_csselr(uint32_t val)
-{
-	/*
-	 * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
-	 * Bit 0 - 0 = data or unified cache, 1 = instruction cache
-	 */
-	asm volatile ("msr csselr_el1, %0" : : "r" (val));
-	isb();	/* ISB to sync the change to CCSIDR_EL1 */
-}
-
-/* read system control register (SCTLR_ELx) */
-static inline uint32_t read_sctlr(uint32_t el)
-{
-	uint32_t val;
-	SWITCH_EL("mrs %0, sctlr_el", : "=r" (val), el);
-	return val;
-}
-
-/* write system control register (SCTLR_ELx) */
-static inline void write_sctlr(uint32_t val, uint32_t el)
-{
-	SWITCH_EL("msr sctlr_el", ", %0" : : "r" (val) : "cc", el);
-	isb();
-}
-
 
 /* dcache clean by virtual address to PoC */
 void dcache_clean_by_va(void const *addr, size_t len);
diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h
new file mode 100644
index 0000000000..8c6198f63f
--- /dev/null
+++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h
@@ -0,0 +1,296 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * lib_helpers.h: All library function prototypes and macros are defined in this
+ * file.
+ */
+
+#define EL0               0
+#define EL1               1
+#define EL2               2
+#define EL3               3
+
+#define CURRENT_EL_MASK   0x3
+#define CURRENT_EL_SHIFT  2
+
+#define DAIF_DBG_BIT      (1<<3)
+#define DAIF_ABT_BIT      (1<<2)
+#define DAIF_IRQ_BIT      (1<<1)
+#define DAIF_FIQ_BIT      (1<<0)
+
+#define SWITCH_CASE_READ(func,var,type)	 do {	\
+	type var = -1;				\
+	uint8_t current_el = get_current_el();	\
+	switch(current_el) {			\
+        case EL1:				\
+		var = func##_el1();		\
+			break;			\
+        case EL2:				\
+		var = func##_el2();		\
+			break;			\
+        case EL3:                               \
+		var = func##_el3();		\
+			break;			\
+	}					\
+	return var;				\
+	} while(0)
+
+#define SWITCH_CASE_WRITE(func,var)	do {   \
+	uint8_t current_el = get_current_el(); \
+	switch(current_el) {		       \
+	case EL1:			       \
+		func##_el1(var);	       \
+			break;		       \
+        case EL2:			       \
+		func##_el2(var);	       \
+			break;		       \
+        case EL3:			       \
+		func##_el3(var);	       \
+			break;		       \
+	}				       \
+	} while(0)
+
+#define SWITCH_CASE_TLBI(func) do {		\
+	uint8_t current_el = get_current_el();	\
+	switch(current_el) {			\
+        case EL1:        			\
+		func##_el1();			\
+			break;			\
+        case EL2:        			\
+		func##_el2();			\
+			break;			\
+        case EL3:        			\
+		func##_el3();			\
+			break;			\
+	}					\
+	} while(0)
+
+/* PSTATE and special purpose register access functions */
+uint32_t raw_read_current_el(void);
+uint32_t get_current_el(void);
+uint32_t raw_read_daif(void);
+void raw_write_daif(uint32_t daif);
+void enable_debug_exceptions(void);
+void enable_serror_exceptions(void);
+void enable_irq(void);
+void enable_fiq(void);
+void disable_debug_exceptions(void);
+void disable_serror_exceptions(void);
+void disable_irq(void);
+void disable_fiq(void);
+uint64_t raw_read_dlr_el0(void);
+void raw_write_dlr_el0(uint64_t dlr_el0);
+uint64_t raw_read_dspsr_el0(void);
+void raw_write_dspsr_el0(uint64_t dspsr_el0);
+uint64_t raw_read_elr_el1(void);
+void raw_write_elr_el1(uint64_t elr_el1);
+uint64_t raw_read_elr_el2(void);
+void raw_write_elr_el2(uint64_t elr_el2);
+uint64_t raw_read_elr_el3(void);
+void raw_write_elr_el3(uint64_t elr_el3);
+uint64_t raw_read_elr_current(void);
+void raw_write_elr_current(uint64_t elr);
+uint32_t raw_read_fpcr(void);
+void raw_write_fpcr(uint32_t fpcr);
+uint32_t raw_read_fpsr(void);
+void raw_write_fpsr(uint32_t fpsr);
+uint32_t raw_read_nzcv(void);
+void raw_write_nzcv(uint32_t nzcv);
+uint64_t raw_read_sp_el0(void);
+void raw_write_sp_el0(uint64_t sp_el0);
+uint64_t raw_read_sp_el1(void);
+void raw_write_sp_el1(uint64_t sp_el1);
+uint64_t raw_read_sp_el2(void);
+void raw_write_sp_el2(uint64_t sp_el2);
+uint32_t raw_read_spsel(void);
+void raw_write_spsel(uint32_t spsel);
+uint64_t raw_read_sp_el3(void);
+void raw_write_sp_el3(uint64_t sp_el3);
+uint32_t raw_read_spsr_abt(void);
+void raw_write_spsr_abt(uint32_t spsr_abt);
+uint32_t raw_read_spsr_el1(void);
+void raw_write_spsr_el1(uint32_t spsr_el1);
+uint32_t raw_read_spsr_el2(void);
+void raw_write_spsr_el2(uint32_t spsr_el2);
+uint32_t raw_read_spsr_el3(void);
+void raw_write_spsr_el3(uint32_t spsr_el3);
+uint32_t raw_read_spsr_current(void);
+void raw_write_spsr_current(uint32_t spsr);
+uint32_t raw_read_spsr_fiq(void);
+void raw_write_spsr_fiq(uint32_t spsr_fiq);
+uint32_t raw_read_spsr_irq(void);
+void raw_write_spsr_irq(uint32_t spsr_irq);
+uint32_t raw_read_spsr_und(void);
+void raw_write_spsr_und(uint32_t spsr_und);
+
+/* System control register access */
+uint32_t raw_read_actlr_el1(void);
+void raw_write_actlr_el1(uint32_t actlr_el1);
+uint32_t raw_read_actlr_el2(void);
+void raw_write_actlr_el2(uint32_t actlr_el2);
+uint32_t raw_read_actlr_el3(void);
+void raw_write_actlr_el3(uint32_t actlr_el3);
+uint32_t raw_read_actlr_current(void);
+void raw_write_actlr_current(uint32_t actlr);
+uint32_t raw_read_afsr0_el1(void);
+void raw_write_afsr0_el1(uint32_t afsr0_el1);
+uint32_t raw_read_afsr0_el2(void);
+void raw_write_afsr0_el2(uint32_t afsr0_el2);
+uint32_t raw_read_afsr0_el3(void);
+void raw_write_afsr0_el3(uint32_t afsr0_el3);
+uint32_t raw_read_afsr0_current(void);
+void raw_write_afsr0_current(uint32_t afsr0);
+uint32_t raw_read_afsr1_el1(void);
+void raw_write_afsr1_el1(uint32_t afsr1_el1);
+uint32_t raw_read_afsr1_el2(void);
+void raw_write_afsr1_el2(uint32_t afsr1_el2);
+uint32_t raw_read_afsr1_el3(void);
+void raw_write_afsr1_el3(uint32_t afsr1_el3);
+uint32_t raw_read_afsr1_current(void);
+void raw_write_afsr1_current(uint32_t afsr1);
+uint32_t raw_read_aidr_el1(void);
+uint64_t raw_read_amair_el1(void);
+void raw_write_amair_el1(uint64_t amair_el1);
+uint64_t raw_read_amair_el2(void);
+void raw_write_amair_el2(uint64_t amair_el2);
+uint64_t raw_read_amair_el3(void);
+void raw_write_amair_el3(uint64_t amair_el3);
+uint64_t raw_read_amair_current(void);
+void raw_write_amair_current(uint64_t amair);
+uint32_t raw_read_ccsidr_el1(void);
+uint32_t raw_read_clidr_el1(void);
+uint32_t raw_read_cpacr_el1(void);
+void raw_write_cpacr_el1(uint32_t cpacr_el1);
+uint32_t raw_read_cptr_el2(void);
+void raw_write_cptr_el2(uint32_t cptr_el2);
+uint32_t raw_read_cptr_el3(void);
+void raw_write_cptr_el3(uint32_t cptr_el3);
+uint32_t raw_read_cptr_current(void);
+void raw_write_cptr_current(uint32_t cptr);
+uint32_t raw_read_csselr_el1(void);
+void raw_write_csselr_el1(uint32_t csselr_el1);
+uint32_t raw_read_ctr_el0(void);
+uint32_t raw_read_esr_el1(void);
+void raw_write_esr_el1(uint32_t esr_el1);
+uint32_t raw_read_esr_el2(void);
+void raw_write_esr_el2(uint32_t esr_el2);
+uint32_t raw_read_esr_el3(void);
+void raw_write_esr_el3(uint32_t esr_el3);
+uint32_t raw_read_esr_current(void);
+void raw_write_esr_current(uint32_t esr);
+uint64_t raw_read_far_el1(void);
+void raw_write_far_el1(uint64_t far_el1);
+uint64_t raw_read_far_el2(void);
+void raw_write_far_el2(uint64_t far_el2);
+uint64_t raw_read_far_el3(void);
+void raw_write_far_el3(uint64_t far_el3);
+uint64_t raw_read_far_current(void);
+void raw_write_far_current(uint64_t far);
+uint64_t raw_read_hcr_el2(void);
+void raw_write_hcr_el2(uint64_t hcr_el2);
+uint64_t raw_read_aa64pfr0_el1(void);
+uint64_t raw_read_mair_el1(void);
+void raw_write_mair_el1(uint64_t mair_el1);
+uint64_t raw_read_mair_el2(void);
+void raw_write_mair_el2(uint64_t mair_el2);
+uint64_t raw_read_mair_el3(void);
+void raw_write_mair_el3(uint64_t mair_el3);
+uint64_t raw_read_mair_current(void);
+void raw_write_mair_current(uint64_t mair);
+uint64_t raw_read_mpidr_el1(void);
+uint32_t raw_read_rmr_el1(void);
+void raw_write_rmr_el1(uint32_t rmr_el1);
+uint32_t raw_read_rmr_el2(void);
+void raw_write_rmr_el2(uint32_t rmr_el2);
+uint32_t raw_read_rmr_el3(void);
+void raw_write_rmr_el3(uint32_t rmr_el3);
+uint32_t raw_read_rmr_current(void);
+void raw_write_rmr_current(uint32_t rmr);
+uint64_t raw_read_rvbar_el1(void);
+void raw_write_rvbar_el1(uint64_t rvbar_el1);
+uint64_t raw_read_rvbar_el2(void);
+void raw_write_rvbar_el2(uint64_t rvbar_el2);
+uint64_t raw_read_rvbar_el3(void);
+void raw_write_rvbar_el3(uint64_t rvbar_el3);
+uint64_t raw_read_rvbar_current(void);
+void raw_write_rvbar_current(uint64_t rvbar);
+uint32_t raw_read_scr_el3(void);
+void raw_write_scr_el3(uint32_t scr_el3);
+uint32_t raw_read_sctlr_el1(void);
+void raw_write_sctlr_el1(uint32_t sctlr_el1);
+uint32_t raw_read_sctlr_el2(void);
+void raw_write_sctlr_el2(uint32_t sctlr_el2);
+uint32_t raw_read_sctlr_el3(void);
+void raw_write_sctlr_el3(uint32_t sctlr_el3);
+uint32_t raw_read_sctlr_current(void);
+void raw_write_sctlr_current(uint32_t sctlr);
+uint64_t raw_read_tcr_el1(void);
+void raw_write_tcr_el1(uint64_t tcr_el1);
+uint32_t raw_read_tcr_el2(void);
+void raw_write_tcr_el2(uint32_t tcr_el2);
+uint32_t raw_read_tcr_el3(void);
+void raw_write_tcr_el3(uint32_t tcr_el3);
+uint64_t raw_read_ttbr0_el1(void);
+void raw_write_ttbr0_el1(uint64_t ttbr0_el1);
+uint64_t raw_read_ttbr0_el2(void);
+void raw_write_ttbr0_el2(uint64_t ttbr0_el2);
+uint64_t raw_read_ttbr0_el3(void);
+void raw_write_ttbr0_el3(uint64_t ttbr0_el3);
+uint64_t raw_read_ttbr0_current(void);
+void raw_write_ttbr0_current(uint64_t ttbr0);
+uint64_t raw_read_ttbr1_el1(void);
+void raw_write_ttbr1_el1(uint64_t ttbr1_el1);
+uint64_t raw_read_vbar_el1(void);
+void raw_write_vbar_el1(uint64_t vbar_el1);
+uint64_t raw_read_vbar_el2(void);
+void raw_write_vbar_el2(uint64_t vbar_el2);
+uint64_t raw_read_vbar_el3(void);
+void raw_write_vbar_el3(uint64_t vbar_el3);
+uint64_t raw_read_vbar_current(void);
+void raw_write_vbar_current(uint64_t vbar);
+
+/* Cache maintenance system instructions */
+void dccisw(uint64_t cisw);
+void dccivac(uint64_t civac);
+void dccsw(uint64_t csw);
+void dccvac(uint64_t cvac);
+void dccvau(uint64_t cvau);
+void dcisw(uint64_t isw);
+void dcivac(uint64_t ivac);
+void dczva(uint64_t zva);
+void iciallu(void);
+void icialluis(void);
+void icivau(uint64_t ivau);
+
+/* TLB maintenance instructions */
+void tlbiall_el1(void);
+void tlbiall_el2(void);
+void tlbiall_el3(void);
+void tlbiall_current(void);
+void tlbiallis_el1(void);
+void tlbiallis_el2(void);
+void tlbiallis_el3(void);
+void tlbiallis_current(void);
+void tlbivaa_el1(uint64_t va);
+
+/* Memory barrier */
+void dmb(void);
+void dsb(void);
+void isb(void);