arm64: Implement generic stage transitions for non-Tegra SoCs

The existing arm64 architecture code has been developed for the Tegra132
and Tegra210 SoCs, which only start their ARM64 cores in ramstage. It
interweaves the stage entry point with code that initializes a CPU (and
should not be run again if that CPU already ran a previous stage). It
also still contains some vestiges of SMP/secmon support (such as setting
up stacks in the BSS instead of using the stage-peristent one from
memlayout).

This patch splits those functions apart and makes the code layout
similar to how things work on ARM32. The default stage_entry() symbol is
a no-op wrapper that just calls main() for the current stage, for the
normal case where a stage ran on the same core as the last one. It can
be overridden by SoC code to support special cases like Tegra.

The CPU initialization code is split out into armv8/cpu.S (similar to
what arm_init_caches() does for ARM32) and called by the default
bootblock entry code. SoCs where a CPU starts up in a later stage can
call the same code from a stage_entry() override instead.

The Tegra132 and Tegra210 code is not touched by this patch to make it
easier to review and validate. A follow-up patch will bring those SoCs
in line with the model.

BRANCH=None
BUG=None
TEST=Booted Oak with a single mmu_init()/mmu_enable(). Built Ryu and
Smaug.

Change-Id: I28302a6ace47e8ab7a736e089f64922cef1a2f93
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12077
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

3 files changed, 8 insertions, 10 deletions

diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index 2ea0a19304..c82cb3f8c7 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -24,11 +24,7 @@ PHDRS
 	to_load PT_LOAD;
 }
 
-#if ENV_BOOTBLOCK
-TARGET(binary)
-#endif
-
-#if ENV_RMODULE
+#if ENV_BOOTBLOCK ||  ENV_RMODULE
 ENTRY(_start)
 #else
 ENTRY(stage_entry)
diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h
index ea4a1ba80c..6db67a9dee 100644
--- a/src/arch/arm64/include/arch/memlayout.h
+++ b/src/arch/arm64/include/arch/memlayout.h
@@ -22,13 +22,13 @@
 	REGION(ttb, addr, size, 4K) \
 	_ = ASSERT(size % 4K == 0, "TTB size must be divisible by 4K!");
 
-/* ARM64 stacks need 16-byte alignment. The ramstage will set up its own stacks
- * in BSS, so this is only used for the SRAM stages. */
-#ifdef __PRE_RAM__
+/* ARM64 stacks need 16-byte alignment. */
+#if !(IS_ENABLED(CONFIG_SOC_NVIDIA_TEGRA132) || \
+      IS_ENABLED(CONFIG_SOC_NVIDIA_TEGRA210))
 #define STACK(addr, size) \
 	REGION(stack, addr, size, 16) \
 	_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc");
-#else
+#else	/* Hack around old Tegra stage_entry.S implementation. TODO: remove */
 #define STACK(addr, size) REGION(preram_stack, addr, size, 16)
 #endif
 
diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h
index 49ea747700..0ec0eea953 100644
--- a/src/arch/arm64/include/armv8/arch/exception.h
+++ b/src/arch/arm64/include/armv8/arch/exception.h
@@ -33,9 +33,11 @@
 #include <arch/transition.h>
 
 /* Initialize the exception handling on the current CPU. */
-void exception_hwinit(void);
 void exception_init(void);
 
+/* Initialize VBAR and SP_EL3. */
+void exception_init_asm(void *exception_stack_end);
+
 /*
  * Order matters for handling return values. The larger the value the higher
  * the precedence.