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| author | Jimmy Huang <jimmy.huang@mediatek.com> | 2015-04-01 18:27:12 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-22 09:01:40 +0200 |
| commit | 6e41523e70b40c92b05c4d52a2b0ddb276e76921 (patch) | |
| tree | 1693bf0a0700ae77fc06c544bb2ec180926c4df9 /src/arch/arm64/stage_entry.S | |
| parent | 5d302c75d84ee71f1e4b7b36a7d67f96b74ee096 (diff) | |
| download | coreboot-6e41523e70b40c92b05c4d52a2b0ddb276e76921.tar.xz | |
arm64: save and restore cntfrq for secondary cpus
CNTFRQ_EL0 can only be set in highest implemented exception level.
Save and restore CNTFRQ_EL0 for secondary cpus in coreboot.
This patch fix the error below:
SANITY CHECK: Unexpected variation in cntfrq. Boot CPU:
0x00000000c65d40, CPU1: 0x00000000000000
BRANCH=none
BUG=none
TEST=boot to kernel on oak board and check secondary cpu's cntfrq.
confirmed cpu1's cntfrq is same as boot cpu's.
Change-Id: I9fbc3c82c2544f0b59ec34b1d631dadf4b9d40eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b47e4e649efc7f79f016522c7d8a240f98225598
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Change-Id: I2d71b0ccfe42e8a30cd1367d10b0f8993431ef8c
Original-Reviewed-on: https://chromium-review.googlesource.com/264914
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9921
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/arm64/stage_entry.S')
| -rw-r--r-- | src/arch/arm64/stage_entry.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index fa2064e708..6fdd20e992 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -190,6 +190,9 @@ ENDPROC(__rmodule_entry) get_element_addr VBAR_INDEX write_current vbar, x0, x1 + get_element_addr CNTFRQ_INDEX + write_el0 cntfrq, x0, x1 + dsb sy isb |