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| author | Aaron Durbin <adurbin@chromium.org> | 2014-09-18 13:48:49 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-28 07:05:35 +0100 |
| commit | dee1996d6c3b4006f4e1d93ab1ffbcb98e30800f (patch) | |
| tree | 44c348c2a3ebab967142f742414dea5b2d7b6d1b /src/arch/arm64/stage_entry.S | |
| parent | b30c9b1c9a676c3b85ac1de9cbc1c5f4424d6297 (diff) | |
| download | coreboot-dee1996d6c3b4006f4e1d93ab1ffbcb98e30800f.tar.xz | |
arm64: provide entry points for BSP and non-BSP
It's helpful to differentiate the startup paths for
the BSP and the non-BSP. Therefore have c_entry
be an 2 element array of function pointers. The
non-BSP paths have an entry point one instruction after
stage/module entry.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: I40bb40462906f1b1eaf2db8584985095e8ac0bae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce10f954041b3fd581ad8a3d82dee567b68637fe
Original-Change-Id: Ia573b1095dca5f69e371bf1ddf6b6df72fa3b52e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218844
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9090
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/arm64/stage_entry.S')
| -rw-r--r-- | src/arch/arm64/stage_entry.S | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 6b8ca7b424..5a5ddabb51 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -105,6 +105,8 @@ ENTRY(arm64_c_environment) /* Get entry point by dereferencing c_entry. */ ldr x1, 1f + /* Retrieve entry in c_entry array using x26 as the index. */ + adds x1, x1, x26, lsl #3 ldr x1, [x1] /* Move back the arguments from x25 to x0 */ mov x0, x25 @@ -114,14 +116,28 @@ ENTRY(arm64_c_environment) .quad c_entry ENDPROC(arm64_c_environment) +/* The first 2 instructions are for BSP and secondary CPUs, + * respectively. x26 holds the index into c_entry array. */ +.macro split_bsp_path + b 2000f + b 2001f + 2000: + mov x26, #0 + b 2002f + 2001: + mov x26, #1 + 2002: +.endm + ENTRY(__rmodule_entry) + split_bsp_path /* Save the arguments to secmon in x25 */ - mov x25, x0 - b arm64_c_environment + mov x25, x0 + b arm64_c_environment ENDPROC(__rmodule_entry) -CPU_RESET_ENTRY(arm64_cpu_startup) - read_current x0, sctlr +ENTRY(_arm64_cpu_startup) + read_current x0, sctlr bic x0, x0, #(1 << 25) /* Little Endian */ bic x0, x0, #(1 << 19) /* XN not enforced */ bic x0, x0, #(1 << 12) /* Disable Instruction Cache */ @@ -129,8 +145,14 @@ CPU_RESET_ENTRY(arm64_cpu_startup) write_current sctlr, x0, x1 isb b arm64_c_environment +ENDPROC(_arm64_cpu_startup) + +CPU_RESET_ENTRY(arm64_cpu_startup) + split_bsp_path + b _arm64_cpu_startup ENDPROC(arm64_cpu_startup) ENTRY(stage_entry) - b arm64_cpu_startup + split_bsp_path + b _arm64_cpu_startup ENDPROC(stage_entry) |