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authorAaron Durbin <adurbin@chromium.org>2014-09-16 22:23:57 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-03-28 07:05:34 +0100
commit4f89d97c06b7e45fb6f3c26e770b0c674a82bb4d (patch)
treed73e4cd8955135b2be8403296643623d0d64b191 /src/arch/arm64/transition_asm.S
parentda1a0778ab27b1b6feffbacaed9aa010b9ab1df1 (diff)
downloadcoreboot-4f89d97c06b7e45fb6f3c26e770b0c674a82bb4d.tar.xz
arm64: exception handler registration
In order to build upon the arm64 exception handlers need to be registered. This provides very basic support to register a handler for a specific exception vector. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel. Change-Id: If046f0736765a2efeb23201c1d2d1f7f7db47dd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a82e5e8d5900ebef16abdb68701be6beeb9ca13a Original-Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218650 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9088 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/arm64/transition_asm.S')
-rw-r--r--src/arch/arm64/transition_asm.S32
1 files changed, 16 insertions, 16 deletions
diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S
index 9f48549028..111efe0a8c 100644
--- a/src/arch/arm64/transition_asm.S
+++ b/src/arch/arm64/transition_asm.S
@@ -77,22 +77,22 @@
*/
ENTRY_WITH_ALIGN(exc_vectors, 11)
-eentry sync_curr_sp0,#0
-eentry irq_curr_sp0,#1
-eentry fiq_curr_sp0,#2
-eentry serror_curr_sp0,#3
-eentry sync_curr_spx,#4
-eentry irq_curr_spx,#5
-eentry fiq_curr_spx,#6
-eentry serror_curr_spx,#7
-eentry sync_lower_64,#8
-eentry irq_lower_64,#9
-eentry fiq_lower_64,#10
-eentry serror_lower_64,#11
-eentry sync_lower_32,#12
-eentry irq_lower_32,#13
-eentry fiq_lower_32,#14
-eentry serror_lower_32,#15
+eentry sync_curr_sp0, #EXC_VID_CUR_SP_EL0_SYNC
+eentry irq_curr_sp0, #EXC_VID_CUR_SP_EL0_IRQ
+eentry fiq_curr_sp0, #EXC_VID_CUR_SP_EL0_FIRQ
+eentry serror_curr_sp0, #EXC_VID_CUR_SP_EL0_SERR
+eentry sync_curr_spx, #EXC_VID_CUR_SP_ELX_SYNC
+eentry irq_curr_spx, #EXC_VID_CUR_SP_ELX_IRQ
+eentry fiq_curr_spx, #EXC_VID_CUR_SP_ELX_FIQ
+eentry serror_curr_spx, #EXC_VID_CUR_SP_ELX_SERR
+eentry sync_lower_64, #EXC_VID_LOW64_SYNC
+eentry irq_lower_64, #EXC_VID_LOW64_IRQ
+eentry fiq_lower_64, #EXC_VID_LOW64_FIQ
+eentry serror_lower_64, #EXC_VID_LOW64_SERR
+eentry sync_lower_32, #EXC_VID_LOW32_SYNC
+eentry irq_lower_32, #EXC_VID_LOW32_IRQ
+eentry fiq_lower_32, #EXC_VID_LOW32_FIQ
+eentry serror_lower_32, #EXC_VID_LOW32_SERR
ENDPROC(exc_vectors)