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authorLogan Carlson <logancarlson@google.com>2017-05-30 15:31:10 -0600
committerMartin Roth <martinroth@google.com>2017-06-02 18:30:53 +0200
commitc058d1c0f8c04a0fca778f70701d7f903754b0b6 (patch)
treee2b54717a77ccb2b14a9314a75be3741850ebdf5 /src/arch/arm64
parentf848ed091e49ab076b5d4dccc7ccff429ecea445 (diff)
downloadcoreboot-c058d1c0f8c04a0fca778f70701d7f903754b0b6.tar.xz
arch/arm: Correct checkpatch errors
Correct whitespace issues in arch/arm and arch/arm64. Enclose complex values in parenthesis. Change-Id: I74b68f485adff1e6f0fa433e51e12b59ccea654b Signed-off-by: Logan Carlson <logancarlson@google.com> Reviewed-on: https://review.coreboot.org/19989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/arch/arm64')
-rw-r--r--src/arch/arm64/armv8/cache.c2
-rw-r--r--src/arch/arm64/armv8/lib/cache.c22
2 files changed, 12 insertions, 12 deletions
diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c
index 4b99cd7830..53aefe0bc4 100644
--- a/src/arch/arm64/armv8/cache.c
+++ b/src/arch/arm64/armv8/cache.c
@@ -85,7 +85,7 @@ static void dcache_op_va(void const *addr, size_t len, enum dcache_op op)
dsb();
while ((void *)line < addr + len) {
- switch(op) {
+ switch (op) {
case OP_DCCIVAC:
dccivac(line);
break;
diff --git a/src/arch/arm64/armv8/lib/cache.c b/src/arch/arm64/armv8/lib/cache.c
index b4ecda656b..0c621ef96d 100644
--- a/src/arch/arm64/armv8/lib/cache.c
+++ b/src/arch/arm64/armv8/lib/cache.c
@@ -23,55 +23,55 @@
void dccisw(uint64_t cisw)
{
- __asm__ __volatile__("dc cisw, %0\n\t" : : "r" (cisw) :"memory");
+ __asm__ __volatile__("dc cisw, %0\n\t" : : "r" (cisw) : "memory");
}
void dccivac(uint64_t civac)
{
- __asm__ __volatile__("dc civac, %0\n\t" : : "r" (civac) :"memory");
+ __asm__ __volatile__("dc civac, %0\n\t" : : "r" (civac) : "memory");
}
void dccsw(uint64_t csw)
{
- __asm__ __volatile__("dc csw, %0\n\t" : : "r" (csw) :"memory");
+ __asm__ __volatile__("dc csw, %0\n\t" : : "r" (csw) : "memory");
}
void dccvac(uint64_t cvac)
{
- __asm__ __volatile__("dc cvac, %0\n\t" : : "r" (cvac) :"memory");
+ __asm__ __volatile__("dc cvac, %0\n\t" : : "r" (cvac) : "memory");
}
void dccvau(uint64_t cvau)
{
- __asm__ __volatile__("dc cvau, %0\n\t" : : "r" (cvau) :"memory");
+ __asm__ __volatile__("dc cvau, %0\n\t" : : "r" (cvau) : "memory");
}
void dcisw(uint64_t isw)
{
- __asm__ __volatile__("dc isw, %0\n\t" : : "r" (isw) :"memory");
+ __asm__ __volatile__("dc isw, %0\n\t" : : "r" (isw) : "memory");
}
void dcivac(uint64_t ivac)
{
- __asm__ __volatile__("dc ivac, %0\n\t" : : "r" (ivac) :"memory");
+ __asm__ __volatile__("dc ivac, %0\n\t" : : "r" (ivac) : "memory");
}
void dczva(uint64_t zva)
{
- __asm__ __volatile__("dc zva, %0\n\t" : : "r" (zva) :"memory");
+ __asm__ __volatile__("dc zva, %0\n\t" : : "r" (zva) : "memory");
}
void iciallu(void)
{
- __asm__ __volatile__("ic iallu\n\t" : : :"memory");
+ __asm__ __volatile__("ic iallu\n\t" : : : "memory");
}
void icialluis(void)
{
- __asm__ __volatile__("ic ialluis\n\t" : : :"memory");
+ __asm__ __volatile__("ic ialluis\n\t" : : : "memory");
}
void icivau(uint64_t ivau)
{
- __asm__ __volatile__("ic ivau, %0\n\t" : : "r" (ivau) :"memory");
+ __asm__ __volatile__("ic ivau, %0\n\t" : : "r" (ivau) : "memory");
}