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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-04-12 10:36:57 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-04 10:05:36 +0000 |
| commit | 23d62dd15c39b3628b102cf6417d476e78ffcdaf (patch) | |
| tree | bccc87c8ea59c7a0663e2882722ab3d2ccd163d0 /src/arch/arm64 | |
| parent | 6f15ba0112c693c129d0425c19af4de6b9231f8a (diff) | |
| download | coreboot-23d62dd15c39b3628b102cf6417d476e78ffcdaf.tar.xz | |
lib/bootmem: Add more bootmem tags
Introduce new bootmem tags to allow more fine grained control over buffer
allocation on various platforms. The new tags are:
BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that
should not be touched by bootmem (by example: stack,
TTB, program, ...).
BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should
not be touched by bootmem.
Starting with this commit all bootmem methods will no longer see memory
that is used by coreboot as usable RAM.
Bootmem changes:
* Introduce a weak function to add platform specific memranges.
* Mark memory allocated by bootmem as BM_TAG_PAYLOAD.
* Assert on failures.
* Add _stack and _program as BM_MEM_RAMSTAGE.
ARMv7 and ARMv8 specific changes:
* Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE.
ARMv7 specific changes:
* Add _ttb_subtables as BM_MEM_RAMSTAGE.
Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/arm64')
| -rw-r--r-- | src/arch/arm64/tables.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index eef6bf2ffd..f36679e67f 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -18,6 +18,7 @@ #include <bootmem.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> +#include <symbols.h> void arch_write_tables(uintptr_t coreboot_table) { @@ -25,6 +26,12 @@ void arch_write_tables(uintptr_t coreboot_table) void bootmem_arch_add_ranges(void) { + bootmem_add_range((uintptr_t)_ttb, _ttb_size, BM_MEM_RAMSTAGE); + + if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER)) + return; + bootmem_add_range((uintptr_t)_postram_cbfs_cache, + _postram_cbfs_cache_size, BM_MEM_RAMSTAGE); } void lb_arch_add_records(struct lb_header *header) |