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authorElyes HAOUAS <ehaouas@noos.fr>2018-06-29 21:41:41 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-07-02 07:39:51 +0000
commite3e3f4f4ed4fee2f739806a81a7323fefe63e96d (patch)
tree56fe3cdaa378ed0e6719fb0b46ca6ec2fa73c110 /src/arch/arm64
parent21b71ce66b89f7bff7959027d971e9a7786bf219 (diff)
downloadcoreboot-e3e3f4f4ed4fee2f739806a81a7323fefe63e96d.tar.xz
src: Get rid of unneeded whitespace
Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/arm64')
-rw-r--r--src/arch/arm64/include/armv8/arch/cache.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h
index b31c3b0153..8e133efcff 100644
--- a/src/arch/arm64/include/armv8/arch/cache.h
+++ b/src/arch/arm64/include/armv8/arch/cache.h
@@ -48,8 +48,8 @@
#define SCTLR_EL1_UMA (1 << 9) /* User mask access */
#define SCTLR_EL1_DZE (1 << 14) /* DC ZVA instruction at EL0 */
#define SCTLR_EL1_UCT (1 << 15) /* CTR_EL0 register EL0 access */
-#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */
-#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */
+#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */
+#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */
#define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */
#define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */