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authorJulius Werner <jwerner@chromium.org>2014-04-04 14:01:15 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-12-15 23:27:41 +0100
commit638015b98b918655fde3ca46cf437c44bd49039f (patch)
treed70b982ca6d9f55e967c2a17d51ded4c487aa626 /src/arch/arm
parent703e507fa0d26766cc96c35e0ef6b10129bcd3b8 (diff)
downloadcoreboot-638015b98b918655fde3ca46cf437c44bd49039f.tar.xz
arm: Fix minor mistake in cache maintenance assembly
Turns out that when you clear 28 bits starting with bit 3, you leave bit 31 standing. Ooops... This shouldn't really matter since that bit is reserved/SBZ in CLIDR anyway, but it's still nice to fix it. This whole thing should really be an AND for clarity anyway in my opinion. Bug found in upstream NetBSD (who would've thought...). BUG=None TEST=Still boots. Change-Id: Ic826e82d58fd1ce984971afea3dfa9296f746d9f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193300 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d270c0ec18b74b272451c456cbf07e99d95896cb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/armv7/cpu.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S
index 5738116c21..589bc07405 100644
--- a/src/arch/arm/armv7/cpu.S
+++ b/src/arch/arm/armv7/cpu.S
@@ -60,7 +60,7 @@
add r2, r3, r3, lsr #1 @ r2 = (level << 1) * 3 / 2
mov r1, r0, lsr r2 @ r1 = cache type
- bfc r1, #3, #28
+ and r1, r1, #7
cmp r1, #2 @ is it data or i&d?
blt 1b @next_level @ nope, skip level