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| author | Logan Carlson <logancarlson@google.com> | 2017-05-30 15:59:02 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-02 18:31:03 +0200 |
| commit | cfbb815efdfbc8c783a6ac631402ab178ee6cb2e (patch) | |
| tree | e1555544d282f7e017bc4400acc5e8b54a966b6e /src/arch/arm | |
| parent | c058d1c0f8c04a0fca778f70701d7f903754b0b6 (diff) | |
| download | coreboot-cfbb815efdfbc8c783a6ac631402ab178ee6cb2e.tar.xz | |
arch/arm/include/armv7/arch: Correct keyword organization in cpu.h
Move the inline keyword in between the static keyword and the return
type.
Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf
Signed-off-by: Logan Carlson <logancarlson@google.com>
Reviewed-on: https://review.coreboot.org/19991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/include/armv7/arch/cpu.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index d70622f959..d9f59d56d1 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -49,7 +49,7 @@ struct cpuinfo_arm { /* Primitives for CPU and MP cores. */ /* read Main Id register (MIDR) */ -inline static uint32_t read_midr(void) +static inline uint32_t read_midr(void) { uint32_t value; asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r"(value)); @@ -57,7 +57,7 @@ inline static uint32_t read_midr(void) } /* read Multiprocessor Affinity Register (MPIDR) */ -inline static uint32_t read_mpidr(void) +static inline uint32_t read_mpidr(void) { uint32_t value; asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r"(value)); @@ -65,7 +65,7 @@ inline static uint32_t read_mpidr(void) } /* read Auxiliary Control Register (ACTLR) */ -inline static uint32_t read_actlr(void) +static inline uint32_t read_actlr(void) { uint32_t val = 0; asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r"(val)); @@ -73,31 +73,31 @@ inline static uint32_t read_actlr(void) } /* write Auxiliary Control Register (ACTLR) */ -inline static void write_actlr(uint32_t val) +static inline void write_actlr(uint32_t val) { asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (val)); } /* wait for interrupt. */ -inline static void wfi(void) +static inline void wfi(void) { asm volatile ("wfi" : : : "memory"); } /* wait for event. */ -inline static void wfe(void) +static inline void wfe(void) { asm volatile ("wfe"); } /* set event (to bring up cores in WFE state). */ -inline static void sev(void) +static inline void sev(void) { asm volatile ("sev"); } /* puts CPU into System mode and disable interrupts. */ -inline static void set_system_mode(void) +static inline void set_system_mode(void) { asm volatile("msr cpsr_c, %0" :: "r"(0x1f | 0xc0)); } |