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| author | Martin Roth <martinroth@google.com> | 2017-06-01 11:39:59 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-07 16:05:16 +0000 |
| commit | 898a77521de97b1e4af9458b82bcc21bc7a6e799 (patch) | |
| tree | 4565d11cc5bbed7729b580424006e1745dc0cfc9 /src/arch/arm | |
| parent | 50bda05e46d5f34f6519a7814e843d1e777ecf10 (diff) | |
| download | coreboot-898a77521de97b1e4af9458b82bcc21bc7a6e799.tar.xz | |
arch/*: Update Kconfig symbol usage
- Update all symbols to use IS_ENABLED()
- Update non-romcc usage to use 'if' instead of '#if' where it
makes sense.
Change-Id: I5a84414d2d1631e35ac91efb67a0d4c1f673bf85
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20005
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/armv7/mmu.c | 2 | ||||
| -rw-r--r-- | src/arch/arm/include/armv7/arch/cache.h | 9 | ||||
| -rw-r--r-- | src/arch/arm/include/armv7/arch/cpu.h | 2 |
3 files changed, 6 insertions, 7 deletions
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 4123bb4d65..6b383ccfb0 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -39,7 +39,7 @@ #include <arch/cache.h> #include <arch/io.h> -#if CONFIG_ARM_LPAE +#if IS_ENABLED(CONFIG_ARM_LPAE) /* See B3.6.2 of ARMv7 Architecture Reference Manual */ /* TODO: Utilize the contiguous hint flag */ #define ATTR_BLOCK (\ diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index 1e6477768c..dd271c5bce 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -134,12 +134,11 @@ static inline void write_mair0(uint32_t val) /* write translation table base register 0 (TTBR0) */ static inline void write_ttbr0(uint32_t val) { -#if CONFIG_ARM_LPAE - asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : : + if (IS_ENABLED(CONFIG_ARM_LPAE)) + asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : : [val] "r" (val), [zero] "r" (0)); -#else - asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory"); -#endif + else + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory"); } /* read translation table base control register (TTBCR) */ diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index d9f59d56d1..b7ef20d5d5 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -33,7 +33,7 @@ struct thread; struct cpu_info { device_t cpu; unsigned long index; -#if CONFIG_COOP_MULTITASKING +#if IS_ENABLED(CONFIG_COOP_MULTITASKING) struct thread *thread; #endif }; |