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authorStefan Reinauer <stefan.reinauer@coreboot.org>2012-12-07 17:15:04 -0800
committerRonald G. Minnich <rminnich@gmail.com>2012-12-08 06:53:19 +0100
commit52db0b984523047da19ca3b41558b9dbf45abad7 (patch)
tree5ed389bb233d5b007593ede56040ccf268e37bbe /src/arch/armv7/Kconfig
parent509f77277cfccdae897f0d369672ce0818ecdf88 (diff)
downloadcoreboot-52db0b984523047da19ca3b41558b9dbf45abad7.tar.xz
WIP: Initial ARMv7 architecture implementation in coreboot
The first ARMv7 CPU we're going to support is the Exynos 5250 used in the Google Snow ChromeBook. Change-Id: I4de8433bbc6202eb8fef2556a11186a3376d411b Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2004 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/armv7/Kconfig')
-rw-r--r--src/arch/armv7/Kconfig52
1 files changed, 52 insertions, 0 deletions
diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig
index 00e6549d98..f92911d6b7 100644
--- a/src/arch/armv7/Kconfig
+++ b/src/arch/armv7/Kconfig
@@ -1,3 +1,55 @@
menu "Architecture (armv7)"
+config SPL_BUILD
+ bool "Build second-phase bootloader (SPL)"
+ default y
+
+config EABI_COMPAT
+ bool "Toolchain is EABI compatible"
+ default n
+
+# Maximum reboot count
+# TODO: Improve description.
+config MAX_REBOOT_CNT
+ int
+ default 3
+
+choice
+ prompt "Bootblock behaviour"
+ default ARM_BOOTBLOCK_SIMPLE
+
+config ARM_BOOTBLOCK_SIMPLE
+ bool "Always load fallback"
+
+config ARM_BOOTBLOCK_NORMAL
+ bool "Switch to normal if non-volatile memory says so"
+
+endchoice
+
+config BOOTBLOCK_SOURCE
+ string
+ default "bootblock_simple.c" if ARM_BOOTBLOCK_SIMPLE
+ default "bootblock_normal.c" if ARM_BOOTBLOCK_NORMAL
+
+config UPDATE_IMAGE
+ bool "Update existing coreboot.rom image"
+ default n
+ depends on TINY_BOOTBLOCK
+ help
+ If this option is enabled, no new coreboot.rom file
+ is created. Instead it is expected that there already
+ is a suitable file for further processing.
+ The bootblock will not be modified.
+
+config BOOTBLOCK_SOC_INIT
+ string
+
+# FIXME: Should cache policy be set on a per-CPU basis?
+# FIXME(dhendrix): Stefan sayz to make a smart decision and not prompt the user.
+config ARM_DCACHE_POLICY_WRITEBACK
+ bool y
+
+config ARM_DCACHE_POLICY_WRITETHROUGH
+ bool n
+
endmenu