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| author | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-07 15:23:45 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-08 22:03:37 +0100 |
| commit | b21eaa74a656fa33f943f76ea0c53ca8374760f6 (patch) | |
| tree | 0271598a31c34c9c36f236fef4760b3932380c08 /src/arch/armv7/Makefile.inc | |
| parent | c2f2bd0a6d00a7f8df4005f148f67373db6d26d6 (diff) | |
| download | coreboot-b21eaa74a656fa33f943f76ea0c53ca8374760f6.tar.xz | |
ARMV7 and Google/Snow: Add exception support code to the ramstage
This is previously used exception code from libpayload.
On startup it installs and then tests an exception handler.
The test is an unaligned memory operation.
Yes, we've seen what might be exceptions in the ramstage, and
it makes sense to handle them. This code is identical in structure
and operation to the previously committed payload exception handler,
though we reserve the right to change it as circumstances require.
The remaining question is whether we need it in romstage.
Change-Id: I24484686c33c9757af8ba171ebae9773828fb69d
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2614
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/arch/armv7/Makefile.inc')
| -rw-r--r-- | src/arch/armv7/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 0595ae246e..e708f6d818 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -158,6 +158,9 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDD $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ # Things that appear in every board +ramstage-y += exception.c +ramstage-y += exception_asm.S + romstage-srcs += $(objgenerated)/crt0.s ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y) |