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authorDavid Hendricks <dhendrix@chromium.org>2013-01-17 15:07:35 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-01-18 00:26:53 +0100
commitfba42a793a67d8910b4ab7fdfb386bcda9896d13 (patch)
tree44edd08ae28e4260ad1cdbad4cccb40be4f840ce /src/arch/armv7/Makefile.inc
parent1c706dc85830a1d91c7ff7c99ac48efd8d085613 (diff)
downloadcoreboot-fba42a793a67d8910b4ab7fdfb386bcda9896d13.tar.xz
Snow bootblock (bloated/debug version)
This is the bloated Snow bootblock which includes: - SPI driver - UART, including requisite I2C, Maxim PMIC, and clock config code. - Adjustments for magic offsets (id section, stack pointer address) This is just a temporary solution until we have romstage loading. Once that happens, we'll rip out all but the code necessary for copying SPI ROM content into SRAM. Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/armv7/Makefile.inc')
-rw-r--r--src/arch/armv7/Makefile.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index ca64f7873f..ecb5aee290 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -259,7 +259,7 @@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootbloc
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld
else
- $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $<
+ $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $< $(LIBGCC_FILE_NAME) -Wl,--end-group
endif
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