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authorStefan Reinauer <stefan.reinauer@coreboot.org>2012-12-07 17:15:04 -0800
committerRonald G. Minnich <rminnich@gmail.com>2012-12-08 06:53:19 +0100
commit52db0b984523047da19ca3b41558b9dbf45abad7 (patch)
tree5ed389bb233d5b007593ede56040ccf268e37bbe /src/arch/armv7/boot
parent509f77277cfccdae897f0d369672ce0818ecdf88 (diff)
downloadcoreboot-52db0b984523047da19ca3b41558b9dbf45abad7.tar.xz
WIP: Initial ARMv7 architecture implementation in coreboot
The first ARMv7 CPU we're going to support is the Exynos 5250 used in the Google Snow ChromeBook. Change-Id: I4de8433bbc6202eb8fef2556a11186a3376d411b Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2004 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/armv7/boot')
-rw-r--r--src/arch/armv7/boot/Makefile.inc13
-rw-r--r--src/arch/armv7/boot/acpi.c791
-rw-r--r--src/arch/armv7/boot/acpigen.c729
-rw-r--r--src/arch/armv7/boot/boot.c189
-rw-r--r--src/arch/armv7/boot/coreboot_table.c711
-rw-r--r--src/arch/armv7/boot/multiboot.c77
-rw-r--r--src/arch/armv7/boot/tables.c100
-rw-r--r--src/arch/armv7/boot/wakeup.S94
8 files changed, 2704 insertions, 0 deletions
diff --git a/src/arch/armv7/boot/Makefile.inc b/src/arch/armv7/boot/Makefile.inc
new file mode 100644
index 0000000000..a0752d6722
--- /dev/null
+++ b/src/arch/armv7/boot/Makefile.inc
@@ -0,0 +1,13 @@
+ramstage-y += boot.c
+ramstage-y += coreboot_table.c
+#ramstage-$(CONFIG_MULTIBOOT) += multiboot.c
+ramstage-y += tables.c
+#ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+#ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c
+#ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
+
+#FIXME(dhendrix): is there anything preventing multiboot from
+#working on ARM?
+
+$(obj)/arch/armv7/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H)
+#$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h
diff --git a/src/arch/armv7/boot/acpi.c b/src/arch/armv7/boot/acpi.c
new file mode 100644
index 0000000000..4d405d9fe0
--- /dev/null
+++ b/src/arch/armv7/boot/acpi.c
@@ -0,0 +1,791 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * coreboot ACPI Table support
+ * written by Stefan Reinauer <stepan@openbios.org>
+ *
+ * Copyright (C) 2004 SUSE LINUX AG
+ * Copyright (C) 2005-2009 coresystems GmbH
+ *
+ * ACPI FADT, FACS, and DSDT table support added by
+ * Nick Barker <nick.barker9@btinternet.com>, and those portions
+ * Copyright (C) 2004 Nick Barker
+ *
+ * Copyright (C) 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ * 2005.9 yhlu add SRAT table generation
+ */
+
+/*
+ * Each system port implementing ACPI has to provide two functions:
+ *
+ * write_acpi_tables()
+ * acpi_dump_apics()
+ *
+ * See Kontron 986LCD-M port for a good example of an ACPI implementation
+ * in coreboot.
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <device/pci.h>
+#include <cbmem.h>
+#include <cpu/x86/lapic_def.h>
+#include <cpu/cpu.h>
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
+#endif
+
+/* FIXME: Kconfig doesn't support overridable defaults :-( */
+#ifndef CONFIG_HPET_MIN_TICKS
+#define CONFIG_HPET_MIN_TICKS 0x1000
+#endif
+
+u8 acpi_checksum(u8 *table, u32 length)
+{
+ u8 ret = 0;
+ while (length--) {
+ ret += *table;
+ table++;
+ }
+ return -ret;
+}
+
+/**
+ * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
+ * and checksum.
+ */
+void acpi_add_table(acpi_rsdp_t *rsdp, void *table)
+{
+ int i, entries_num;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt = NULL;
+
+ /* The RSDT is mandatory... */
+ rsdt = (acpi_rsdt_t *)rsdp->rsdt_address;
+
+ /* ...while the XSDT is not. */
+ if (rsdp->xsdt_address)
+ xsdt = (acpi_xsdt_t *)((u32)rsdp->xsdt_address);
+
+ /* This should always be MAX_ACPI_TABLES. */
+ entries_num = ARRAY_SIZE(rsdt->entry);
+
+ for (i = 0; i < entries_num; i++) {
+ if (rsdt->entry[i] == 0)
+ break;
+ }
+
+ if (i >= entries_num) {
+ printk(BIOS_ERR, "ACPI: Error: Could not add ACPI table, "
+ "too many tables.\n");
+ return;
+ }
+
+ /* Add table to the RSDT. */
+ rsdt->entry[i] = (u32)table;
+
+ /* Fix RSDT length or the kernel will assume invalid entries. */
+ rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1));
+
+ /* Re-calculate checksum. */
+ rsdt->header.checksum = 0; /* Hope this won't get optimized away */
+ rsdt->header.checksum = acpi_checksum((u8 *)rsdt, rsdt->header.length);
+
+ /*
+ * And now the same thing for the XSDT. We use the same index as for
+ * now we want the XSDT and RSDT to always be in sync in coreboot.
+ */
+ if (xsdt) {
+ /* Add table to the XSDT. */
+ xsdt->entry[i] = (u64)(u32)table;
+
+ /* Fix XSDT length. */
+ xsdt->header.length = sizeof(acpi_header_t) +
+ (sizeof(u64) * (i + 1));
+
+ /* Re-calculate checksum. */
+ xsdt->header.checksum = 0;
+ xsdt->header.checksum = acpi_checksum((u8 *)xsdt,
+ xsdt->header.length);
+ }
+
+ printk(BIOS_DEBUG, "ACPI: added table %d/%d, length now %d\n",
+ i + 1, entries_num, rsdt->header.length);
+}
+
+int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base,
+ u16 seg_nr, u8 start, u8 end)
+{
+ mmconfig->base_address = base;
+ mmconfig->base_reserved = 0;
+ mmconfig->pci_segment_group_number = seg_nr;
+ mmconfig->start_bus_number = start;
+ mmconfig->end_bus_number = end;
+
+ return sizeof(acpi_mcfg_mmconfig_t);
+}
+
+int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
+{
+ lapic->type = 0; /* Local APIC structure */
+ lapic->length = sizeof(acpi_madt_lapic_t);
+ lapic->flags = (1 << 0); /* Processor/LAPIC enabled */
+ lapic->processor_id = cpu;
+ lapic->apic_id = apic;
+
+ return lapic->length;
+}
+
+unsigned long acpi_create_madt_lapics(unsigned long current)
+{
+ device_t cpu;
+ int index = 0;
+
+ for (cpu = all_devices; cpu; cpu = cpu->next) {
+ if ((cpu->path.type != DEVICE_PATH_APIC) ||
+ (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
+ continue;
+ }
+ if (!cpu->enabled)
+ continue;
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
+ index, cpu->path.apic.apic_id);
+ index++;
+ }
+
+ return current;
+}
+
+int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,
+ u32 gsi_base)
+{
+ ioapic->type = 1; /* I/O APIC structure */
+ ioapic->length = sizeof(acpi_madt_ioapic_t);
+ ioapic->reserved = 0x00;
+ ioapic->gsi_base = gsi_base;
+ ioapic->ioapic_id = id;
+ ioapic->ioapic_addr = addr;
+
+ return ioapic->length;
+}
+
+int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride,
+ u8 bus, u8 source, u32 gsirq, u16 flags)
+{
+ irqoverride->type = 2; /* Interrupt source override */
+ irqoverride->length = sizeof(acpi_madt_irqoverride_t);
+ irqoverride->bus = bus;
+ irqoverride->source = source;
+ irqoverride->gsirq = gsirq;
+ irqoverride->flags = flags;
+
+ return irqoverride->length;
+}
+
+int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu,
+ u16 flags, u8 lint)
+{
+ lapic_nmi->type = 4; /* Local APIC NMI structure */
+ lapic_nmi->length = sizeof(acpi_madt_lapic_nmi_t);
+ lapic_nmi->flags = flags;
+ lapic_nmi->processor_id = cpu;
+ lapic_nmi->lint = lint;
+
+ return lapic_nmi->length;
+}
+
+void acpi_create_madt(acpi_madt_t *madt)
+{
+ acpi_header_t *header = &(madt->header);
+ unsigned long current = (unsigned long)madt + sizeof(acpi_madt_t);
+
+ memset((void *)madt, 0, sizeof(acpi_madt_t));
+
+ /* Fill out header fields. */
+ memcpy(header->signature, "APIC", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_madt_t);
+ header->revision = 1; /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
+
+ madt->lapic_addr = LOCAL_APIC_ADDR;
+ madt->flags = 0x1; /* PCAT_COMPAT */
+
+ current = acpi_fill_madt(current);
+
+ /* (Re)calculate length and checksum. */
+ header->length = current - (unsigned long)madt;
+
+ header->checksum = acpi_checksum((void *)madt, header->length);
+}
+
+/* MCFG is defined in the PCI Firmware Specification 3.0. */
+void acpi_create_mcfg(acpi_mcfg_t *mcfg)
+{
+ acpi_header_t *header = &(mcfg->header);
+ unsigned long current = (unsigned long)mcfg + sizeof(acpi_mcfg_t);
+
+ memset((void *)mcfg, 0, sizeof(acpi_mcfg_t));
+
+ /* Fill out header fields. */
+ memcpy(header->signature, "MCFG", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_mcfg_t);
+ header->revision = 1;
+
+ current = acpi_fill_mcfg(current);
+
+ /* (Re)calculate length and checksum. */
+ header->length = current - (unsigned long)mcfg;
+ header->checksum = acpi_checksum((void *)mcfg, header->length);
+}
+
+/*
+ * This can be overriden by platform ACPI setup code, if it calls
+ * acpi_create_ssdt_generator().
+ */
+unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(
+ unsigned long current, const char *oem_table_id)
+{
+ return current;
+}
+
+void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
+{
+ unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
+
+ memset((void *)ssdt, 0, sizeof(acpi_header_t));
+
+ memcpy(&ssdt->signature, "SSDT", 4);
+ ssdt->revision = 2; /* ACPI 1.0/2.0: ?, ACPI 3.0/4.0: 2 */
+ memcpy(&ssdt->oem_id, OEM_ID, 6);
+ memcpy(&ssdt->oem_table_id, oem_table_id, 8);
+ ssdt->oem_revision = 42;
+ memcpy(&ssdt->asl_compiler_id, ASLC, 4);
+ ssdt->asl_compiler_revision = 42;
+ ssdt->length = sizeof(acpi_header_t);
+
+ acpigen_set_current((char *) current);
+ current = acpi_fill_ssdt_generator(current, oem_table_id);
+
+ /* (Re)calculate length and checksum. */
+ ssdt->length = current - (unsigned long)ssdt;
+ ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
+}
+
+int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic)
+{
+ memset((void *)lapic, 0, sizeof(acpi_srat_lapic_t));
+
+ lapic->type = 0; /* Processor local APIC/SAPIC affinity structure */
+ lapic->length = sizeof(acpi_srat_lapic_t);
+ lapic->flags = (1 << 0); /* Enabled (the use of this structure). */
+ lapic->proximity_domain_7_0 = node;
+ /* TODO: proximity_domain_31_8, local SAPIC EID, clock domain. */
+ lapic->apic_id = apic;
+
+ return lapic->length;
+}
+
+int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek,
+ u32 flags)
+{
+ mem->type = 1; /* Memory affinity structure */
+ mem->length = sizeof(acpi_srat_mem_t);
+ mem->base_address_low = (basek << 10);
+ mem->base_address_high = (basek >> (32 - 10));
+ mem->length_low = (sizek << 10);
+ mem->length_high = (sizek >> (32 - 10));
+ mem->proximity_domain = node;
+ mem->flags = flags;
+
+ return mem->length;
+}
+
+/* http://www.microsoft.com/whdc/system/sysinternals/sratdwn.mspx */
+void acpi_create_srat(acpi_srat_t *srat)
+{
+ acpi_header_t *header = &(srat->header);
+ unsigned long current = (unsigned long)srat + sizeof(acpi_srat_t);
+
+ memset((void *)srat, 0, sizeof(acpi_srat_t));
+
+ /* Fill out header fields. */
+ memcpy(header->signature, "SRAT", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_srat_t);
+ header->revision = 1; /* ACPI 1.0: N/A, 2.0: 1, 3.0: 2, 4.0: 3 */
+
+ srat->resv = 1; /* Spec: Reserved to 1 for backwards compatibility. */
+
+ current = acpi_fill_srat(current);
+
+ /* (Re)calculate length and checksum. */
+ header->length = current - (unsigned long)srat;
+ header->checksum = acpi_checksum((void *)srat, header->length);
+}
+
+unsigned long __attribute__((weak)) acpi_fill_dmar(unsigned long current)
+{
+ return current;
+}
+
+void acpi_create_dmar(acpi_dmar_t *dmar)
+{
+ acpi_header_t *header = &(dmar->header);
+ unsigned long current = (unsigned long)dmar + sizeof(acpi_dmar_t);
+
+ memset((void *)dmar, 0, sizeof(acpi_dmar_t));
+
+ /* Fill out header fields. */
+ memcpy(header->signature, "DMAR", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_dmar_t);
+ header->revision = 1;
+
+ dmar->host_address_width = 40 - 1; /* FIXME: == MTRR size? */
+ dmar->flags = 0;
+
+ current = acpi_fill_dmar(current);
+
+ /* (Re)calculate length and checksum. */
+ header->length = current - (unsigned long)dmar;
+ header->checksum = acpi_checksum((void *)dmar, header->length);
+}
+
+unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags,
+ u16 segment, u32 bar)
+{
+ dmar_entry_t *drhd = (dmar_entry_t *)current;
+ memset(drhd, 0, sizeof(*drhd));
+ drhd->type = DMAR_DRHD;
+ drhd->length = sizeof(*drhd); /* will be fixed up later */
+ drhd->flags = flags;
+ drhd->segment = segment;
+ drhd->bar = bar;
+
+ return drhd->length;
+}
+
+void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current)
+{
+ dmar_entry_t *drhd = (dmar_entry_t *)base;
+ drhd->length = current - base;
+}
+
+unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 segment,
+ u8 dev, u8 fn)
+{
+ dev_scope_t *ds = (dev_scope_t *)current;
+ memset(ds, 0, sizeof(*ds));
+ ds->type = SCOPE_PCI_ENDPOINT;
+ ds->length = sizeof(*ds) + 2; /* we don't support longer paths yet */
+ ds->start_bus = segment;
+ ds->path[0].dev = dev;
+ ds->path[0].fn = fn;
+
+ return ds->length;
+}
+
+/* http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/slit.pdf */
+void acpi_create_slit(acpi_slit_t *slit)
+{
+ acpi_header_t *header = &(slit->header);
+ unsigned long current = (unsigned long)slit + sizeof(acpi_slit_t);
+
+ memset((void *)slit, 0, sizeof(acpi_slit_t));
+
+ /* Fill out header fields. */
+ memcpy(header->signature, "SLIT", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_slit_t);
+ header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */
+
+ current = acpi_fill_slit(current);
+
+ /* (Re)calculate length and checksum. */
+ header->length = current - (unsigned long)slit;
+ header->checksum = acpi_checksum((void *)slit, header->length);
+}
+
+/* http://www.intel.com/hardwaredesign/hpetspec_1.pdf */
+void acpi_create_hpet(acpi_hpet_t *hpet)
+{
+ acpi_header_t *header = &(hpet->header);
+ acpi_addr_t *addr = &(hpet->addr);
+
+ memset((void *)hpet, 0, sizeof(acpi_hpet_t));
+
+ /* Fill out header fields. */
+ memcpy(header->signature, "HPET", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_hpet_t);
+ header->revision = 1; /* Currently 1. Table added in ACPI 2.0. */
+
+ /* Fill out HPET address. */
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff;
+ addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
+
+ hpet->id = *(unsigned int*)CONFIG_HPET_ADDRESS;
+ hpet->number = 0;
+ hpet->min_tick = CONFIG_HPET_MIN_TICKS;
+
+ header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t));
+}
+
+void acpi_create_facs(acpi_facs_t *facs)
+{
+ memset((void *)facs, 0, sizeof(acpi_facs_t));
+
+ memcpy(facs->signature, "FACS", 4);
+ facs->length = sizeof(acpi_facs_t);
+ facs->hardware_signature = 0;
+ facs->firmware_waking_vector = 0;
+ facs->global_lock = 0;
+ facs->flags = 0;
+ facs->x_firmware_waking_vector_l = 0;
+ facs->x_firmware_waking_vector_h = 0;
+ facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
+}
+
+void acpi_write_rsdt(acpi_rsdt_t *rsdt)
+{
+ acpi_header_t *header = &(rsdt->header);
+
+ /* Fill out header fields. */
+ memcpy(header->signature, "RSDT", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_rsdt_t);
+ header->revision = 1; /* ACPI 1.0/2.0/3.0/4.0: 1 */
+
+ /* Entries are filled in later, we come with an empty set. */
+
+ /* Fix checksum. */
+ header->checksum = acpi_checksum((void *)rsdt, sizeof(acpi_rsdt_t));
+}
+
+void acpi_write_xsdt(acpi_xsdt_t *xsdt)
+{
+ acpi_header_t *header = &(xsdt->header);
+
+ /* Fill out header fields. */
+ memcpy(header->signature, "XSDT", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_xsdt_t);
+ header->revision = 1; /* ACPI 1.0: N/A, 2.0/3.0/4.0: 1 */
+
+ /* Entries are filled in later, we come with an empty set. */
+
+ /* Fix checksum. */
+ header->checksum = acpi_checksum((void *)xsdt, sizeof(acpi_xsdt_t));
+}
+
+void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt)
+{
+ memset(rsdp, 0, sizeof(acpi_rsdp_t));
+
+ memcpy(rsdp->signature, RSDP_SIG, 8);
+ memcpy(rsdp->oem_id, OEM_ID, 6);
+
+ rsdp->length = sizeof(acpi_rsdp_t);
+ rsdp->rsdt_address = (u32)rsdt;
+
+ /*
+ * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2.
+ *
+ * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
+ * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
+ * revision 0).
+ */
+ if (xsdt == NULL) {
+ rsdp->revision = 0;
+ } else {
+ rsdp->xsdt_address = (u64)(u32)xsdt;
+ rsdp->revision = 2;
+ }
+
+ /* Calculate checksums. */
+ rsdp->checksum = acpi_checksum((void *)rsdp, 20);
+ rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t));
+}
+
+unsigned long __attribute__((weak)) acpi_fill_hest(acpi_hest_t *hest)
+{
+ return (unsigned long)hest;
+}
+
+unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 data_len)
+{
+ acpi_header_t *header = &(hest->header);
+ acpi_hest_hen_t *hen;
+ void *pos;
+ u16 len;
+
+ pos = esd;
+ memset(pos, 0, sizeof(acpi_hest_esd_t));
+ len = 0;
+ esd->type = type; /* MCE */
+ esd->source_id = hest->error_source_count;
+ esd->flags = 0; /* FIRMWARE_FIRST */
+ esd->enabled = 1;
+ esd->prealloc_erecords = 1;
+ esd->max_section_per_record = 0x1;
+
+ len += sizeof(acpi_hest_esd_t);
+ pos = esd + 1;
+
+ switch (type) {
+ case 0: /* MCE */
+ break;
+ case 1: /* CMC */
+ hen = (acpi_hest_hen_t *) (pos);
+ memset(pos, 0, sizeof(acpi_hest_hen_t));
+ hen->type = 3; /* SCI? */
+ hen->length = sizeof(acpi_hest_hen_t);
+ hen->conf_we = 0; /* Configuration Write Enable. */
+ hen->poll_interval = 0;
+ hen->vector = 0;
+ hen->sw2poll_threshold_val = 0;
+ hen->sw2poll_threshold_win = 0;
+ hen->error_threshold_val = 0;
+ hen->error_threshold_win = 0;
+ len += sizeof(acpi_hest_hen_t);
+ pos = hen + 1;
+ break;
+ case 2: /* NMI */
+ case 6: /* AER Root Port */
+ case 7: /* AER Endpoint */
+ case 8: /* AER Bridge */
+ case 9: /* Generic Hardware Error Source. */
+ /* TODO: */
+ break;
+ default:
+ printk(BIOS_DEBUG, "Invalid type of Error Source.");
+ break;
+ }
+ hest->error_source_count ++;
+
+ memcpy(pos, data, data_len);
+ len += data_len;
+ header->length += len;
+
+ return len;
+}
+
+/* ACPI 4.0 */
+void acpi_write_hest(acpi_hest_t *hest)
+{
+ acpi_header_t *header = &(hest->header);
+
+ memset(hest, 0, sizeof(acpi_hest_t));
+
+ memcpy(header->signature, "HEST", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->length += sizeof(acpi_hest_t);
+ header->revision = 1;
+
+ acpi_fill_hest(hest);
+
+ /* Calculate checksums. */
+ header->checksum = acpi_checksum((void *)hest, header->length);
+}
+
+#if CONFIG_HAVE_ACPI_RESUME
+void suspend_resume(void)
+{
+ void *wake_vec;
+
+ /* If we happen to be resuming find wakeup vector and jump to OS. */
+ wake_vec = acpi_find_wakeup_vector();
+ if (wake_vec) {
+#if CONFIG_HAVE_SMI_HANDLER
+ u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS);
+
+ /* Restore GNVS pointer in SMM if found */
+ if (gnvs_address && *gnvs_address) {
+ printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n",
+ *gnvs_address);
+ smm_setup_structures((void *)*gnvs_address, NULL, NULL);
+ }
+#endif
+
+ /* Call mainboard resume handler first, if defined. */
+ if (mainboard_suspend_resume)
+ mainboard_suspend_resume();
+ post_code(POST_OS_RESUME);
+ acpi_jump_to_wakeup(wake_vec);
+ }
+}
+
+/* This is to be filled by SB code - startup value what was found. */
+u8 acpi_slp_type = 0;
+
+static int acpi_is_wakeup(void)
+{
+ /* Both resume from S2 and resume from S3 restart at CPU reset */
+ return (acpi_slp_type == 3 || acpi_slp_type == 2);
+}
+
+static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp)
+{
+ if (strncmp((char *)rsdp, RSDP_SIG, sizeof(RSDP_SIG) - 1) != 0)
+ return NULL;
+
+ printk(BIOS_DEBUG, "Looking on %p for valid checksum\n", rsdp);
+
+ if (acpi_checksum((void *)rsdp, 20) != 0)
+ return NULL;
+ printk(BIOS_DEBUG, "Checksum 1 passed\n");
+
+ if ((rsdp->revision > 1) && (acpi_checksum((void *)rsdp,
+ rsdp->length) != 0))
+ return NULL;
+ printk(BIOS_DEBUG, "Checksum 2 passed all OK\n");
+
+ return rsdp;
+}
+
+static acpi_rsdp_t *rsdp;
+
+void *acpi_get_wakeup_rsdp(void)
+{
+ return rsdp;
+}
+
+void *acpi_find_wakeup_vector(void)
+{
+ char *p, *end;
+ acpi_rsdt_t *rsdt;
+ acpi_facs_t *facs;
+ acpi_fadt_t *fadt;
+ void *wake_vec;
+ int i;
+
+ rsdp = NULL;
+
+ if (!acpi_is_wakeup())
+ return NULL;
+
+ printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n");
+
+ /* Find RSDP. */
+ for (p = (char *)0xe0000; p < (char *)0xfffff; p += 16) {
+ if ((rsdp = valid_rsdp((acpi_rsdp_t *)p)))
+ break;
+ }
+
+ if (rsdp == NULL)
+ return NULL;
+
+ printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp);
+ rsdt = (acpi_rsdt_t *) rsdp->rsdt_address;
+
+ end = (char *)rsdt + rsdt->header.length;
+ printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end);
+
+ for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) {
+ fadt = (acpi_fadt_t *)rsdt->entry[i];
+ if (strncmp((char *)fadt, "FACP", 4) == 0)
+ break;
+ fadt = NULL;
+ }
+
+ if (fadt == NULL)
+ return NULL;
+
+ printk(BIOS_DEBUG, "FADT found at %p\n", fadt);
+ facs = (acpi_facs_t *)fadt->firmware_ctrl;
+
+ if (facs == NULL) {
+ printk(BIOS_DEBUG, "No FACS found, wake up from S3 not "
+ "possible.\n");
+ return NULL;
+ }
+
+ printk(BIOS_DEBUG, "FACS found at %p\n", facs);
+ wake_vec = (void *)facs->firmware_waking_vector;
+ printk(BIOS_DEBUG, "OS waking vector is %p\n", wake_vec);
+
+ return wake_vec;
+}
+
+#if CONFIG_SMP
+extern char *lowmem_backup;
+extern char *lowmem_backup_ptr;
+extern int lowmem_backup_size;
+#endif
+
+#define WAKEUP_BASE 0x600
+
+void (*acpi_do_wakeup)(u32 vector, u32 backup_source, u32 backup_target,
+ u32 backup_size) __attribute__((regparm(0))) = (void *)WAKEUP_BASE;
+
+extern unsigned char __wakeup, __wakeup_size;
+
+void acpi_jump_to_wakeup(void *vector)
+{
+ u32 acpi_backup_memory = (u32)cbmem_find(CBMEM_ID_RESUME);
+
+ if (!acpi_backup_memory) {
+ printk(BIOS_WARNING, "ACPI: Backup memory missing. "
+ "No S3 resume.\n");
+ return;
+ }
+
+#if CONFIG_SMP
+ // FIXME: This should go into the ACPI backup memory, too. No pork saussages.
+ /*
+ * Just restore the SMP trampoline and continue with wakeup on
+ * assembly level.
+ */
+ memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
+#endif
+
+ /* Copy wakeup trampoline in place. */
+ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_add_now(TS_ACPI_WAKE_JUMP);
+#endif
+
+ acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE,
+ HIGH_MEMORY_SAVE);
+}
+#endif
+
+void acpi_save_gnvs(u32 gnvs_address)
+{
+ u32 *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+ if (gnvs)
+ *gnvs = gnvs_address;
+}
diff --git a/src/arch/armv7/boot/acpigen.c b/src/arch/armv7/boot/acpigen.c
new file mode 100644
index 0000000000..47845a01a6
--- /dev/null
+++ b/src/arch/armv7/boot/acpigen.c
@@ -0,0 +1,729 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* how many nesting we support */
+#define ACPIGEN_LENSTACK_SIZE 10
+
+/* if you need to change this, change the acpigen_write_f and
+ acpigen_patch_len */
+
+#define ACPIGEN_MAXLEN 0xfff
+
+#include <string.h>
+#include <arch/acpigen.h>
+#include <console/console.h>
+#include <device/device.h>
+
+static char *gencurrent;
+
+char *len_stack[ACPIGEN_LENSTACK_SIZE];
+int ltop = 0;
+
+int acpigen_write_len_f(void)
+{
+ ASSERT(ltop < (ACPIGEN_LENSTACK_SIZE - 1))
+ len_stack[ltop++] = gencurrent;
+ acpigen_emit_byte(0);
+ acpigen_emit_byte(0);
+ return 2;
+}
+
+void acpigen_patch_len(int len)
+{
+ ASSERT(len <= ACPIGEN_MAXLEN)
+ ASSERT(ltop > 0)
+ char *p = len_stack[--ltop];
+ /* generate store length for 0xfff max */
+ p[0] = (0x40 | (len & 0xf));
+ p[1] = (len >> 4 & 0xff);
+
+}
+
+void acpigen_set_current(char *curr)
+{
+ gencurrent = curr;
+}
+
+char *acpigen_get_current(void)
+{
+ return gencurrent;
+}
+
+int acpigen_emit_byte(unsigned char b)
+{
+ (*gencurrent++) = b;
+ return 1;
+}
+
+int acpigen_write_package(int nr_el)
+{
+ int len;
+ /* package op */
+ acpigen_emit_byte(0x12);
+ len = acpigen_write_len_f();
+ acpigen_emit_byte(nr_el);
+ return len + 2;
+}
+
+int acpigen_write_byte(unsigned int data)
+{
+ /* byte op */
+ acpigen_emit_byte(0xa);
+ acpigen_emit_byte(data & 0xff);
+ return 2;
+}
+
+int acpigen_write_dword(unsigned int data)
+{
+ /* dword op */
+ acpigen_emit_byte(0xc);
+ acpigen_emit_byte(data & 0xff);
+ acpigen_emit_byte((data >> 8) & 0xff);
+ acpigen_emit_byte((data >> 16) & 0xff);
+ acpigen_emit_byte((data >> 24) & 0xff);
+ return 5;
+}
+
+int acpigen_write_qword(uint64_t data)
+{
+ /* qword op */
+ acpigen_emit_byte(0xe);
+ acpigen_emit_byte(data & 0xff);
+ acpigen_emit_byte((data >> 8) & 0xff);
+ acpigen_emit_byte((data >> 16) & 0xff);
+ acpigen_emit_byte((data >> 24) & 0xff);
+ acpigen_emit_byte((data >> 32) & 0xff);
+ acpigen_emit_byte((data >> 40) & 0xff);
+ acpigen_emit_byte((data >> 48) & 0xff);
+ acpigen_emit_byte((data >> 56) & 0xff);
+ return 9;
+}
+
+int acpigen_write_name_byte(const char *name, uint8_t val)
+{
+ int len;
+ len = acpigen_write_name(name);
+ len += acpigen_write_byte(val);
+ return len;
+}
+
+int acpigen_write_name_dword(const char *name, uint32_t val)
+{
+ int len;
+ len = acpigen_write_name(name);
+ len += acpigen_write_dword(val);
+ return len;
+}
+
+int acpigen_write_name_qword(const char *name, uint64_t val)
+{
+ int len;
+ len = acpigen_write_name(name);
+ len += acpigen_write_qword(val);
+ return len;
+}
+
+int acpigen_emit_stream(const char *data, int size)
+{
+ int i;
+ for (i = 0; i < size; i++) {
+ acpigen_emit_byte(data[i]);
+ }
+ return size;
+}
+
+/* The NameString are bit tricky, each element can be 4 chars, if
+ less its padded with underscore. Check 18.2.2 and 18.4
+ and 5.3 of ACPI specs 3.0 for details
+*/
+
+static int acpigen_emit_simple_namestring(const char *name) {
+ int i, len = 0;
+ char ud[] = "____";
+ for (i = 0; i < 4; i++) {
+ if ((name[i] == '\0') || (name[i] == '.')) {
+ len += acpigen_emit_stream(ud, 4 - i);
+ break;
+ } else {
+ len += acpigen_emit_byte(name[i]);
+ }
+ }
+ return len;
+}
+
+static int acpigen_emit_double_namestring(const char *name, int dotpos) {
+ int len = 0;
+ /* mark dual name prefix */
+ len += acpigen_emit_byte(0x2e);
+ len += acpigen_emit_simple_namestring(name);
+ len += acpigen_emit_simple_namestring(&name[dotpos + 1]);
+ return len;
+}
+
+static int acpigen_emit_multi_namestring(const char *name) {
+ int len = 0, count = 0;
+ unsigned char *pathlen;
+ /* mark multi name prefix */
+ len += acpigen_emit_byte(0x2f);
+ len += acpigen_emit_byte(0x0);
+ pathlen = ((unsigned char *) acpigen_get_current()) - 1;
+
+ while (name[0] != '\0') {
+ len += acpigen_emit_simple_namestring(name);
+ /* find end or next entity */
+ while ((name[0] != '.') && (name[0] != '\0'))
+ name++;
+ /* forward to next */
+ if (name[0] == '.')
+ name++;
+ count++;
+ }
+
+ pathlen[0] = count;
+ return len;
+}
+
+
+int acpigen_emit_namestring(const char *namepath) {
+ int dotcount = 0, i;
+ int dotpos = 0;
+ int len = 0;
+
+ /* we can start with a \ */
+ if (namepath[0] == '\\') {
+ len += acpigen_emit_byte('\\');
+ namepath++;
+ }
+
+ /* and there can be any number of ^ */
+ while (namepath[0] == '^') {
+ len += acpigen_emit_byte('^');
+ namepath++;
+ }
+
+ ASSERT(namepath[0] != '\0');
+
+ i = 0;
+ while (namepath[i] != '\0') {
+ if (namepath[i] == '.') {
+ dotcount++;
+ dotpos = i;
+ }
+ i++;
+ }
+
+ if (dotcount == 0) {
+ len += acpigen_emit_simple_namestring(namepath);
+ } else if (dotcount == 1) {
+ len += acpigen_emit_double_namestring(namepath, dotpos);
+ } else {
+ len += acpigen_emit_multi_namestring(namepath);
+ }
+ return len;
+}
+
+int acpigen_write_name(const char *name)
+{
+ int len;
+ /* name op */
+ len = acpigen_emit_byte(0x8);
+ return len + acpigen_emit_namestring(name);
+}
+
+int acpigen_write_scope(const char *name)
+{
+ int len;
+ /* scope op */
+ len = acpigen_emit_byte(0x10);
+ len += acpigen_write_len_f();
+ return len + acpigen_emit_namestring(name);
+}
+
+int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
+{
+/*
+ Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len)
+ {
+*/
+ char pscope[16];
+ int len;
+ /* processor op */
+ acpigen_emit_byte(0x5b);
+ acpigen_emit_byte(0x83);
+ len = acpigen_write_len_f();
+
+ sprintf(pscope, "\\_PR.CPU%x", (unsigned int) cpuindex);
+ len += acpigen_emit_namestring(pscope);
+ acpigen_emit_byte(cpuindex);
+ acpigen_emit_byte(pblock_addr & 0xff);
+ acpigen_emit_byte((pblock_addr >> 8) & 0xff);
+ acpigen_emit_byte((pblock_addr >> 16) & 0xff);
+ acpigen_emit_byte((pblock_addr >> 24) & 0xff);
+ acpigen_emit_byte(pblock_len);
+ return 6 + 2 + len;
+}
+
+int acpigen_write_empty_PCT(void)
+{
+/*
+ Name (_PCT, Package (0x02)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+*/
+ static char stream[] = {
+ 0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C, /* 00000030 "0._PCT.," */
+ 0x02, 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, /* 00000038 "........" */
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000040 "........" */
+ 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14, /* 00000048 "....y..." */
+ 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, 0x00, 0x00, /* 00000050 "........" */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000058 "........" */
+ 0x00, 0x79, 0x00
+ };
+ return acpigen_emit_stream(stream, ARRAY_SIZE(stream));
+}
+
+int acpigen_write_empty_PTC(void)
+{
+/*
+ Name (_PTC, Package (0x02)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+*/
+ int len, nlen, rlen;
+ acpi_addr_t addr = {
+ .space_id = ACPI_ADDRESS_SPACE_FIXED,
+ .bit_width = 0,
+ .bit_offset = 0,
+ {
+ .resv = 0
+ },
+ .addrl = 0,
+ .addrh = 0,
+ };
+
+ nlen = acpigen_write_name("_PTC");
+ len = acpigen_write_package(2);
+
+ /* ControlRegister */
+ rlen = acpigen_write_resourcetemplate_header();
+ rlen += acpigen_write_register(&addr);
+ len += acpigen_write_resourcetemplate_footer(rlen);
+ len += rlen;
+
+ /* StatusRegister */
+ rlen = acpigen_write_resourcetemplate_header();
+ rlen += acpigen_write_register(&addr);
+ len += acpigen_write_resourcetemplate_footer(rlen);
+ len += rlen;
+
+ acpigen_patch_len(len - 1);
+ return len + nlen;
+}
+
+/* generates a func with max supported P states */
+int acpigen_write_PPC(u8 nr)
+{
+/*
+ Method (_PPC, 0, NotSerialized)
+ {
+ Return (nr)
+ }
+*/
+ int len;
+ /* method op */
+ acpigen_emit_byte(0x14);
+ len = acpigen_write_len_f();
+ len += acpigen_emit_namestring("_PPC");
+ /* no fnarg */
+ acpigen_emit_byte(0x00);
+ /* return */
+ acpigen_emit_byte(0xa4);
+ /* arg */
+ len += acpigen_write_byte(nr);
+ /* add all single bytes */
+ len += 3;
+ acpigen_patch_len(len - 1);
+ return len;
+}
+
+/* generates a func with max supported P states */
+int acpigen_write_PPC_NVS(void)
+{
+/*
+ Method (_PPC, 0, NotSerialized)
+ {
+ Return (PPCM)
+ }
+*/
+ int len;
+ /* method op */
+ acpigen_emit_byte(0x14);
+ len = acpigen_write_len_f();
+ len += acpigen_emit_namestring("_PPC");
+ /* no fnarg */
+ acpigen_emit_byte(0x00);
+ /* return */
+ acpigen_emit_byte(0xa4);
+ /* arg */
+ len += acpigen_emit_namestring("PPCM");
+ /* add all single bytes */
+ len += 3;
+ acpigen_patch_len(len - 1);
+ return len;
+}
+
+int acpigen_write_TPC(const char *gnvs_tpc_limit)
+{
+/*
+ // Sample _TPC method
+ Method (_TPC, 0, NotSerialized)
+ {
+ Return (\TLVL)
+ }
+ */
+ int len;
+
+ len = acpigen_emit_byte(0x14); /* MethodOp */
+ len += acpigen_write_len_f(); /* PkgLength */
+ len += acpigen_emit_namestring("_TPC");
+ len += acpigen_emit_byte(0x00); /* No Arguments */
+ len += acpigen_emit_byte(0xa4); /* ReturnOp */
+ len += acpigen_emit_namestring(gnvs_tpc_limit);
+ acpigen_patch_len(len - 1);
+ return len;
+}
+
+int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
+ u32 busmLat, u32 control, u32 status)
+{
+ int len;
+ len = acpigen_write_package(6);
+ len += acpigen_write_dword(coreFreq);
+ len += acpigen_write_dword(power);
+ len += acpigen_write_dword(transLat);
+ len += acpigen_write_dword(busmLat);
+ len += acpigen_write_dword(control);
+ len += acpigen_write_dword(status);
+ // pkglen without the len opcode
+ acpigen_patch_len(len - 1);
+
+ printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n",
+ coreFreq, power, control, status);
+
+ return len;
+}
+
+int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype)
+{
+ int len, lenh, lenp;
+ lenh = acpigen_write_name("_PSD");
+ lenp = acpigen_write_package(1);
+ len = acpigen_write_package(5);
+ len += acpigen_write_byte(5); // 5 values
+ len += acpigen_write_byte(0); // revision 0
+ len += acpigen_write_dword(domain);
+ len += acpigen_write_dword(coordtype);
+ len += acpigen_write_dword(numprocs);
+ acpigen_patch_len(len - 1);
+ len += lenp;
+ acpigen_patch_len(len - 1);
+ return len + lenh;
+}
+
+int acpigen_write_CST_package_entry(acpi_cstate_t *cstate)
+{
+ int len, len0;
+ char *start, *end;
+
+ len0 = acpigen_write_package(4);
+ len = acpigen_write_resourcetemplate_header();
+ start = acpigen_get_current();
+ acpigen_write_register(&cstate->resource);
+ end = acpigen_get_current();
+ len += end - start;
+ len += acpigen_write_resourcetemplate_footer(len);
+ len += len0;
+ len += acpigen_write_dword(cstate->ctype);
+ len += acpigen_write_dword(cstate->latency);
+ len += acpigen_write_dword(cstate->power);
+ acpigen_patch_len(len - 1);
+ return len;
+}
+
+int acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries)
+{
+ int len, lenh, lenp, i;
+ lenh = acpigen_write_name("_CST");
+ lenp = acpigen_write_package(nentries+1);
+ len = acpigen_write_dword(nentries);
+
+ for (i = 0; i < nentries; i++)
+ len += acpigen_write_CST_package_entry(cstate + i);
+
+ len += lenp;
+ acpigen_patch_len(len - 1);
+ return len + lenh;
+}
+
+int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list)
+{
+/*
+ Sample _TSS package with 100% and 50% duty cycles
+ Name (_TSS, Package (0x02)
+ {
+ Package(){100, 1000, 0, 0x00, 0)
+ Package(){50, 520, 0, 0x18, 0)
+ })
+ */
+ int i, len, plen, nlen;
+ acpi_tstate_t *tstate = tstate_list;
+
+ nlen = acpigen_write_name("_TSS");
+ plen = acpigen_write_package(entries);
+
+ for (i = 0; i < entries; i++) {
+ len = acpigen_write_package(5);
+ len += acpigen_write_dword(tstate->percent);
+ len += acpigen_write_dword(tstate->power);
+ len += acpigen_write_dword(tstate->latency);
+ len += acpigen_write_dword(tstate->control);
+ len += acpigen_write_dword(tstate->status);
+ acpigen_patch_len(len - 1);
+ tstate++;
+ plen += len;
+ }
+
+ acpigen_patch_len(plen - 1);
+ return plen + nlen;
+}
+
+int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype)
+{
+ int len, lenh, lenp;
+ lenh = acpigen_write_name("_TSD");
+ lenp = acpigen_write_package(1);
+ len = acpigen_write_package(5);
+ len += acpigen_write_byte(5); // 5 values
+ len += acpigen_write_byte(0); // revision 0
+ len += acpigen_write_dword(domain);
+ len += acpigen_write_dword(coordtype);
+ len += acpigen_write_dword(numprocs);
+ acpigen_patch_len(len - 1);
+ len += lenp;
+ acpigen_patch_len(len - 1);
+ return len + lenh;
+}
+
+
+
+int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size)
+{
+ /*
+ * acpi 4.0 section 6.4.3.4: 32-Bit Fixed Memory Range Descriptor
+ * Byte 0:
+ * Bit7 : 1 => big item
+ * Bit6-0: 0000110 (0x6) => 32-bit fixed memory
+ */
+ acpigen_emit_byte(0x86);
+ /* Byte 1+2: length (0x0009) */
+ acpigen_emit_byte(0x09);
+ acpigen_emit_byte(0x00);
+ /* bit1-7 are ignored */
+ acpigen_emit_byte(readwrite ? 0x01 : 0x00);
+ acpigen_emit_byte(base & 0xff);
+ acpigen_emit_byte((base >> 8) & 0xff);
+ acpigen_emit_byte((base >> 16) & 0xff);
+ acpigen_emit_byte((base >> 24) & 0xff);
+ acpigen_emit_byte(size & 0xff);
+ acpigen_emit_byte((size >> 8) & 0xff);
+ acpigen_emit_byte((size >> 16) & 0xff);
+ acpigen_emit_byte((size >> 24) & 0xff);
+ return 12;
+}
+
+int acpigen_write_register(acpi_addr_t *addr)
+{
+ acpigen_emit_byte(0x82); /* Register Descriptor */
+ acpigen_emit_byte(0x0c); /* Register Length 7:0 */
+ acpigen_emit_byte(0x00); /* Register Length 15:8 */
+ acpigen_emit_byte(addr->space_id); /* Address Space ID */
+ acpigen_emit_byte(addr->bit_width); /* Register Bit Width */
+ acpigen_emit_byte(addr->bit_offset); /* Register Bit Offset */
+ acpigen_emit_byte(addr->resv); /* Register Access Size */
+ acpigen_emit_byte(addr->addrl & 0xff); /* Register Address Low */
+ acpigen_emit_byte((addr->addrl >> 8) & 0xff);
+ acpigen_emit_byte((addr->addrl >> 16) & 0xff);
+ acpigen_emit_byte((addr->addrl >> 24) & 0xff);
+ acpigen_emit_byte(addr->addrh & 0xff); /* Register Address High */
+ acpigen_emit_byte((addr->addrh >> 8) & 0xff);
+ acpigen_emit_byte((addr->addrh >> 16) & 0xff);
+ acpigen_emit_byte((addr->addrh >> 24) & 0xff);
+ return 15;
+}
+
+int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16)
+{
+ /*
+ * acpi 4.0 section 6.4.2.6: I/O Port Descriptor
+ * Byte 0:
+ * Bit7 : 0 => small item
+ * Bit6-3: 1000 (0x8) => I/O port descriptor
+ * Bit2-0: 111 (0x7) => 7 Bytes long
+ */
+ acpigen_emit_byte(0x47);
+ /* does the device decode all 16 or just 10 bits? */
+ /* bit1-7 are ignored */
+ acpigen_emit_byte(decode16 ? 0x01 : 0x00);
+ /* minimum base address the device may be configured for */
+ acpigen_emit_byte(min & 0xff);
+ acpigen_emit_byte((min >> 8) & 0xff);
+ /* maximum base address the device may be configured for */
+ acpigen_emit_byte(max & 0xff);
+ acpigen_emit_byte((max >> 8) & 0xff);
+ /* alignment for min base */
+ acpigen_emit_byte(align & 0xff);
+ acpigen_emit_byte(len & 0xff);
+ return 8;
+}
+
+int acpigen_write_resourcetemplate_header(void)
+{
+ int len;
+ /*
+ * A ResourceTemplate() is a Buffer() with a
+ * (Byte|Word|DWord) containing the length, followed by one or more
+ * resource items, terminated by the end tag
+ * (small item 0xf, len 1)
+ */
+ len = acpigen_emit_byte(0x11); /* Buffer opcode */
+ len += acpigen_write_len_f();
+ len += acpigen_emit_byte(0x0b); /* Word opcode */
+ len_stack[ltop++] = acpigen_get_current();
+ len += acpigen_emit_byte(0x00);
+ len += acpigen_emit_byte(0x00);
+ return len;
+}
+
+int acpigen_write_resourcetemplate_footer(int len)
+{
+ char *p = len_stack[--ltop];
+ /*
+ * end tag (acpi 4.0 Section 6.4.2.8)
+ * 0x79 <checksum>
+ * 0x00 is treated as a good checksum according to the spec
+ * and is what iasl generates.
+ */
+ len += acpigen_emit_byte(0x79);
+ len += acpigen_emit_byte(0x00);
+ /* patch len word */
+ p[0] = (len-6) & 0xff;
+ p[1] = ((len-6) >> 8) & 0xff;
+ /* patch len field */
+ acpigen_patch_len(len-1);
+ return 2;
+}
+
+static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev,
+ struct resource *res)
+{
+ acpigen_write_mem32fixed(0, res->base, res->size);
+}
+
+static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev,
+ struct resource *res)
+{
+ resource_t base = res->base;
+ resource_t size = res->size;
+ while (size > 0) {
+ resource_t sz = size > 255 ? 255 : size;
+ acpigen_write_io16(base, base, 0, sz, 1);
+ size -= sz;
+ base += sz;
+ }
+}
+
+int acpigen_write_mainboard_resource_template(void)
+{
+ int len;
+ char *start;
+ char *end;
+ len = acpigen_write_resourcetemplate_header();
+ start = acpigen_get_current();
+
+ /* Add reserved memory ranges */
+ search_global_resources(
+ IORESOURCE_MEM | IORESOURCE_RESERVE,
+ IORESOURCE_MEM | IORESOURCE_RESERVE,
+ acpigen_add_mainboard_rsvd_mem32, 0);
+
+ /* Add reserved io ranges */
+ search_global_resources(
+ IORESOURCE_IO | IORESOURCE_RESERVE,
+ IORESOURCE_IO | IORESOURCE_RESERVE,
+ acpigen_add_mainboard_rsvd_io, 0);
+
+ end = acpigen_get_current();
+ len += end-start;
+ len += acpigen_write_resourcetemplate_footer(len);
+ return len;
+}
+
+int acpigen_write_mainboard_resources(const char *scope, const char *name)
+{
+ int len;
+ len = acpigen_write_scope(scope);
+ len += acpigen_write_name(name);
+ len += acpigen_write_mainboard_resource_template();
+ acpigen_patch_len(len - 1);
+ return len;
+}
diff --git a/src/arch/armv7/boot/boot.c b/src/arch/armv7/boot/boot.c
new file mode 100644
index 0000000000..722fca540f
--- /dev/null
+++ b/src/arch/armv7/boot/boot.c
@@ -0,0 +1,189 @@
+#include <console/console.h>
+#include <ip_checksum.h>
+#include <boot/elf.h>
+#include <boot/elf_boot.h>
+#include <string.h>
+#include <cpu/x86/multiboot.h>
+
+
+#ifndef CMD_LINE
+#define CMD_LINE ""
+#endif
+
+
+
+#define UPSZ(X) ((sizeof(X) + 3) &~3)
+
+static struct {
+ Elf_Bhdr hdr;
+ Elf_Nhdr ft_hdr;
+ unsigned char ft_desc[UPSZ(FIRMWARE_TYPE)];
+ Elf_Nhdr bl_hdr;
+ unsigned char bl_desc[UPSZ(BOOTLOADER)];
+ Elf_Nhdr blv_hdr;
+ unsigned char blv_desc[UPSZ(BOOTLOADER_VERSION)];
+ Elf_Nhdr cmd_hdr;
+ unsigned char cmd_desc[UPSZ(CMD_LINE)];
+} elf_boot_notes = {
+ .hdr = {
+ .b_signature = 0x0E1FB007,
+ .b_size = sizeof(elf_boot_notes),
+ .b_checksum = 0,
+ .b_records = 4,
+ },
+ .ft_hdr = {
+ .n_namesz = 0,
+ .n_descsz = sizeof(FIRMWARE_TYPE),
+ .n_type = EBN_FIRMWARE_TYPE,
+ },
+ .ft_desc = FIRMWARE_TYPE,
+ .bl_hdr = {
+ .n_namesz = 0,
+ .n_descsz = sizeof(BOOTLOADER),
+ .n_type = EBN_BOOTLOADER_NAME,
+ },
+ .bl_desc = BOOTLOADER,
+ .blv_hdr = {
+ .n_namesz = 0,
+ .n_descsz = sizeof(BOOTLOADER_VERSION),
+ .n_type = EBN_BOOTLOADER_VERSION,
+ },
+ .blv_desc = BOOTLOADER_VERSION,
+ .cmd_hdr = {
+ .n_namesz = 0,
+ .n_descsz = sizeof(CMD_LINE),
+ .n_type = EBN_COMMAND_LINE,
+ },
+ .cmd_desc = CMD_LINE,
+};
+
+
+int elf_check_arch(Elf_ehdr *ehdr)
+{
+ return (
+ ((ehdr->e_machine == EM_386) || (ehdr->e_machine == EM_486)) &&
+ (ehdr->e_ident[EI_CLASS] == ELFCLASS32) &&
+ (ehdr->e_ident[EI_DATA] == ELFDATA2LSB)
+ );
+
+}
+
+void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size)
+{
+ extern unsigned char _ram_seg, _eram_seg;
+ unsigned long lb_start, lb_size;
+ unsigned long adjust, adjusted_boot_notes;
+
+ elf_boot_notes.hdr.b_checksum =
+ compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes));
+
+ lb_start = (unsigned long)&_ram_seg;
+ lb_size = (unsigned long)(&_eram_seg - &_ram_seg);
+ adjust = buffer + size - lb_start;
+
+ adjusted_boot_notes = (unsigned long)&elf_boot_notes;
+ adjusted_boot_notes += adjust;
+
+ printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry);
+ printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start);
+ printk(BIOS_SPEW, "lb_size = 0x%08lx\n", lb_size);
+ printk(BIOS_SPEW, "adjust = 0x%08lx\n", adjust);
+ printk(BIOS_SPEW, "buffer = 0x%08lx\n", buffer);
+ printk(BIOS_SPEW, " elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes);
+ printk(BIOS_SPEW, "adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes);
+
+ /* FIXME(dhendrix): port code to jump to kernel here... */
+#if 0
+ /* Jump to kernel */
+ __asm__ __volatile__(
+ " cld \n\t"
+ /* Save the callee save registers... */
+ " pushl %%esi\n\t"
+ " pushl %%edi\n\t"
+ " pushl %%ebx\n\t"
+ /* Save the parameters I was passed */
+ " pushl $0\n\t" /* 20 adjust */
+ " pushl %0\n\t" /* 16 lb_start */
+ " pushl %1\n\t" /* 12 buffer */
+ " pushl %2\n\t" /* 8 lb_size */
+ " pushl %3\n\t" /* 4 entry */
+ " pushl %4\n\t" /* 0 elf_boot_notes */
+ /* Compute the adjustment */
+ " xorl %%eax, %%eax\n\t"
+ " subl 16(%%esp), %%eax\n\t"
+ " addl 12(%%esp), %%eax\n\t"
+ " addl 8(%%esp), %%eax\n\t"
+ " movl %%eax, 20(%%esp)\n\t"
+ /* Place a copy of coreboot in its new location */
+ /* Move ``longs'' the coreboot size is 4 byte aligned */
+ " movl 12(%%esp), %%edi\n\t"
+ " addl 8(%%esp), %%edi\n\t"
+ " movl 16(%%esp), %%esi\n\t"
+ " movl 8(%%esp), %%ecx\n\n"
+ " shrl $2, %%ecx\n\t"
+ " rep movsl\n\t"
+
+ /* Adjust the stack pointer to point into the new coreboot image */
+ " addl 20(%%esp), %%esp\n\t"
+ /* Adjust the instruction pointer to point into the new coreboot image */
+ " movl $1f, %%eax\n\t"
+ " addl 20(%%esp), %%eax\n\t"
+ " jmp *%%eax\n\t"
+ "1: \n\t"
+
+ /* Copy the coreboot bounce buffer over coreboot */
+ /* Move ``longs'' the coreboot size is 4 byte aligned */
+ " movl 16(%%esp), %%edi\n\t"
+ " movl 12(%%esp), %%esi\n\t"
+ " movl 8(%%esp), %%ecx\n\t"
+ " shrl $2, %%ecx\n\t"
+ " rep movsl\n\t"
+
+ /* Now jump to the loaded image */
+ " movl %5, %%eax\n\t"
+ " movl 0(%%esp), %%ebx\n\t"
+ " call *4(%%esp)\n\t"
+
+ /* The loaded image returned? */
+ " cli \n\t"
+ " cld \n\t"
+
+ /* Copy the saved copy of coreboot where coreboot runs */
+ /* Move ``longs'' the coreboot size is 4 byte aligned */
+ " movl 16(%%esp), %%edi\n\t"
+ " movl 12(%%esp), %%esi\n\t"
+ " addl 8(%%esp), %%esi\n\t"
+ " movl 8(%%esp), %%ecx\n\t"
+ " shrl $2, %%ecx\n\t"
+ " rep movsl\n\t"
+
+ /* Adjust the stack pointer to point into the old coreboot image */
+ " subl 20(%%esp), %%esp\n\t"
+
+ /* Adjust the instruction pointer to point into the old coreboot image */
+ " movl $1f, %%eax\n\t"
+ " subl 20(%%esp), %%eax\n\t"
+ " jmp *%%eax\n\t"
+ "1: \n\t"
+
+ /* Drop the parameters I was passed */
+ " addl $24, %%esp\n\t"
+
+ /* Restore the callee save registers */
+ " popl %%ebx\n\t"
+ " popl %%edi\n\t"
+ " popl %%esi\n\t"
+
+ ::
+ "ri" (lb_start), "ri" (buffer), "ri" (lb_size),
+ "ri" (entry),
+#if CONFIG_MULTIBOOT
+ "ri"(mbi), "ri" (MB_MAGIC2)
+#else
+ "ri"(adjusted_boot_notes), "ri" (0x0E1FB007)
+#endif
+ );
+#endif
+}
+
+
diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c
new file mode 100644
index 0000000000..9f67da0e1b
--- /dev/null
+++ b/src/arch/armv7/boot/coreboot_table.c
@@ -0,0 +1,711 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003-2004 Eric Biederman
+ * Copyright (C) 2005-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <ip_checksum.h>
+#include <boot/tables.h>
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+#include <string.h>
+#include <version.h>
+#include <device/device.h>
+#include <stdlib.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#if CONFIG_USE_OPTION_TABLE
+#include <option_table.h>
+#endif
+#if CONFIG_CHROMEOS
+#include <arch/acpi.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#endif
+
+static struct lb_header *lb_table_init(unsigned long addr)
+{
+ struct lb_header *header;
+
+ /* 16 byte align the address */
+ addr += 15;
+ addr &= ~15;
+
+ header = (void *)addr;
+ header->signature[0] = 'L';
+ header->signature[1] = 'B';
+ header->signature[2] = 'I';
+ header->signature[3] = 'O';
+ header->header_bytes = sizeof(*header);
+ header->header_checksum = 0;
+ header->table_bytes = 0;
+ header->table_checksum = 0;
+ header->table_entries = 0;
+ return header;
+}
+
+static struct lb_record *lb_first_record(struct lb_header *header)
+{
+ struct lb_record *rec;
+ rec = (void *)(((char *)header) + sizeof(*header));
+ return rec;
+}
+
+static struct lb_record *lb_last_record(struct lb_header *header)
+{
+ struct lb_record *rec;
+ rec = (void *)(((char *)header) + sizeof(*header) + header->table_bytes);
+ return rec;
+}
+
+#if 0
+static struct lb_record *lb_next_record(struct lb_record *rec)
+{
+ rec = (void *)(((char *)rec) + rec->size);
+ return rec;
+}
+#endif
+
+static struct lb_record *lb_new_record(struct lb_header *header)
+{
+ struct lb_record *rec;
+ rec = lb_last_record(header);
+ if (header->table_entries) {
+ header->table_bytes += rec->size;
+ }
+ rec = lb_last_record(header);
+ header->table_entries++;
+ rec->tag = LB_TAG_UNUSED;
+ rec->size = sizeof(*rec);
+ return rec;
+}
+
+
+static struct lb_memory *lb_memory(struct lb_header *header)
+{
+ struct lb_record *rec;
+ struct lb_memory *mem;
+ rec = lb_new_record(header);
+ mem = (struct lb_memory *)rec;
+ mem->tag = LB_TAG_MEMORY;
+ mem->size = sizeof(*mem);
+ return mem;
+}
+
+static struct lb_serial *lb_serial(struct lb_header *header)
+{
+#if CONFIG_CONSOLE_SERIAL8250
+ struct lb_record *rec;
+ struct lb_serial *serial;
+ rec = lb_new_record(header);
+ serial = (struct lb_serial *)rec;
+ serial->tag = LB_TAG_SERIAL;
+ serial->size = sizeof(*serial);
+ serial->type = LB_SERIAL_TYPE_IO_MAPPED;
+ serial->baseaddr = CONFIG_TTYS0_BASE;
+ serial->baud = CONFIG_TTYS0_BAUD;
+ return serial;
+#elif CONFIG_CONSOLE_SERIAL8250MEM
+ if (uartmem_getbaseaddr()) {
+ struct lb_record *rec;
+ struct lb_serial *serial;
+ rec = lb_new_record(header);
+ serial = (struct lb_serial *)rec;
+ serial->tag = LB_TAG_SERIAL;
+ serial->size = sizeof(*serial);
+ serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial->baseaddr = uartmem_getbaseaddr();
+ serial->baud = CONFIG_TTYS0_BAUD;
+ return serial;
+ } else {
+ return NULL;
+ }
+#else
+ return NULL;
+#endif
+}
+
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \
+ CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG
+static void add_console(struct lb_header *header, u16 consoletype)
+{
+ struct lb_console *console;
+
+ console = (struct lb_console *)lb_new_record(header);
+ console->tag = LB_TAG_CONSOLE;
+ console->size = sizeof(*console);
+ console->type = consoletype;
+}
+#endif
+
+static void lb_console(struct lb_header *header)
+{
+#if CONFIG_CONSOLE_SERIAL8250
+ add_console(header, LB_TAG_CONSOLE_SERIAL8250);
+#endif
+#if CONFIG_CONSOLE_SERIAL8250MEM
+ add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM);
+#endif
+#if CONFIG_CONSOLE_LOGBUF
+ add_console(header, LB_TAG_CONSOLE_LOGBUF);
+#endif
+#if CONFIG_USBDEBUG
+ add_console(header, LB_TAG_CONSOLE_EHCI);
+#endif
+}
+
+static void lb_framebuffer(struct lb_header *header)
+{
+#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE
+ void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
+ int vbe_mode_info_valid(void);
+
+ // If there isn't any mode info to put in the table, don't ask for it
+ // to be filled with junk.
+ if (!vbe_mode_info_valid())
+ return;
+ struct lb_framebuffer *framebuffer;
+ framebuffer = (struct lb_framebuffer *)lb_new_record(header);
+ framebuffer->tag = LB_TAG_FRAMEBUFFER;
+ framebuffer->size = sizeof(*framebuffer);
+ fill_lb_framebuffer(framebuffer);
+#endif
+}
+
+#if CONFIG_CHROMEOS
+static void lb_gpios(struct lb_header *header)
+{
+ struct lb_gpios *gpios;
+ gpios = (struct lb_gpios *)lb_new_record(header);
+ gpios->tag = LB_TAG_GPIO;
+ gpios->size = sizeof(*gpios);
+ gpios->count = 0;
+ fill_lb_gpios(gpios);
+}
+
+static void lb_vdat(struct lb_header *header)
+{
+ struct lb_vdat* vdat;
+
+ vdat = (struct lb_vdat *)lb_new_record(header);
+ vdat->tag = LB_TAG_VDAT;
+ vdat->size = sizeof(*vdat);
+ acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size);
+}
+
+static void lb_vbnv(struct lb_header *header)
+{
+ struct lb_vbnv* vbnv;
+
+ vbnv = (struct lb_vbnv *)lb_new_record(header);
+ vbnv->tag = LB_TAG_VBNV;
+ vbnv->size = sizeof(*vbnv);
+ vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14;
+ vbnv->vbnv_size = CONFIG_VBNV_SIZE;
+}
+#endif
+
+static void add_cbmem_pointers(struct lb_header *header)
+{
+ /*
+ * These CBMEM sections' addresses are included in the coreboot table
+ * with the appropriate tags.
+ */
+ const struct section_id {
+ int cbmem_id;
+ int table_tag;
+ } section_ids[] = {
+ {CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS},
+ {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE}
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(section_ids); i++) {
+ const struct section_id *sid = section_ids + i;
+ struct lb_cbmem_ref *cbmem_ref;
+ void *cbmem_addr = cbmem_find(sid->cbmem_id);
+
+ if (!cbmem_addr)
+ continue; /* This section is not present */
+
+ cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header);
+ if (!cbmem_ref) {
+ printk(BIOS_ERR, "No more room in coreboot table!\n");
+ break;
+ }
+ cbmem_ref->tag = sid->table_tag;
+ cbmem_ref->size = sizeof(*cbmem_ref);
+ cbmem_ref->cbmem_addr = cbmem_addr;
+ }
+}
+
+static struct lb_mainboard *lb_mainboard(struct lb_header *header)
+{
+ struct lb_record *rec;
+ struct lb_mainboard *mainboard;
+ rec = lb_new_record(header);
+ mainboard = (struct lb_mainboard *)rec;
+ mainboard->tag = LB_TAG_MAINBOARD;
+
+ mainboard->size = (sizeof(*mainboard) +
+ strlen(mainboard_vendor) + 1 +
+ strlen(mainboard_part_number) + 1 +
+ 3) & ~3;
+
+ mainboard->vendor_idx = 0;
+ mainboard->part_number_idx = strlen(mainboard_vendor) + 1;
+
+ memcpy(mainboard->strings + mainboard->vendor_idx,
+ mainboard_vendor, strlen(mainboard_vendor) + 1);
+ memcpy(mainboard->strings + mainboard->part_number_idx,
+ mainboard_part_number, strlen(mainboard_part_number) + 1);
+
+ return mainboard;
+}
+
+#if CONFIG_USE_OPTION_TABLE
+static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
+{
+ struct lb_record *rec;
+ struct cmos_checksum *cmos_checksum;
+ rec = lb_new_record(header);
+ cmos_checksum = (struct cmos_checksum *)rec;
+ cmos_checksum->tag = LB_TAG_OPTION_CHECKSUM;
+
+ cmos_checksum->size = (sizeof(*cmos_checksum));
+
+ cmos_checksum->range_start = LB_CKS_RANGE_START * 8;
+ cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7;
+ cmos_checksum->location = LB_CKS_LOC * 8;
+ cmos_checksum->type = CHECKSUM_PCBIOS;
+
+ return cmos_checksum;
+}
+#endif
+
+static void lb_strings(struct lb_header *header)
+{
+ static const struct {
+ uint32_t tag;
+ const char *string;
+ } strings[] = {
+ { LB_TAG_VERSION, coreboot_version, },
+ { LB_TAG_EXTRA_VERSION, coreboot_extra_version, },
+ { LB_TAG_BUILD, coreboot_build, },
+ { LB_TAG_COMPILE_TIME, coreboot_compile_time, },
+ { LB_TAG_COMPILE_BY, coreboot_compile_by, },
+ { LB_TAG_COMPILE_HOST, coreboot_compile_host, },
+ { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
+ { LB_TAG_COMPILER, coreboot_compiler, },
+ { LB_TAG_LINKER, coreboot_linker, },
+ { LB_TAG_ASSEMBLER, coreboot_assembler, },
+ };
+ unsigned int i;
+ for(i = 0; i < ARRAY_SIZE(strings); i++) {
+ struct lb_string *rec;
+ size_t len;
+ rec = (struct lb_string *)lb_new_record(header);
+ len = strlen(strings[i].string);
+ rec->tag = strings[i].tag;
+ rec->size = (sizeof(*rec) + len + 1 + 3) & ~3;
+ memcpy(rec->string, strings[i].string, len+1);
+ }
+
+}
+
+#if CONFIG_WRITE_HIGH_TABLES
+static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header)
+{
+ struct lb_record *rec;
+ struct lb_forward *forward;
+ rec = lb_new_record(header);
+ forward = (struct lb_forward *)rec;
+ forward->tag = LB_TAG_FORWARD;
+ forward->size = sizeof(*forward);
+ forward->forward = (uint64_t)(unsigned long)next_header;
+ return forward;
+}
+#endif
+
+/* FIXME(dhendrix): used to be static void lb_memory_range(), but compiler
+ started complaining since it shares a name with a non-static struct. ugh. */
+static void new_lb_memory_range(struct lb_memory *mem,
+ uint32_t type, uint64_t start, uint64_t size)
+{
+ int entries;
+ entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
+ mem->map[entries].start = pack_lb64(start);
+ mem->map[entries].size = pack_lb64(size);
+ mem->map[entries].type = type;
+ mem->size += sizeof(mem->map[0]);
+}
+
+static void lb_reserve_table_memory(struct lb_header *head)
+{
+ struct lb_record *last_rec;
+ struct lb_memory *mem;
+ uint64_t start;
+ uint64_t end;
+ int i, entries;
+
+ last_rec = lb_last_record(head);
+ mem = get_lb_mem();
+ start = (unsigned long)head;
+ end = (unsigned long)last_rec;
+ entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
+ /* Resize the right two memory areas so this table is in
+ * a reserved area of memory. Everything has been carefully
+ * setup so that is all we need to do.
+ */
+ for(i = 0; i < entries; i++ ) {
+ uint64_t map_start = unpack_lb64(mem->map[i].start);
+ uint64_t map_end = map_start + unpack_lb64(mem->map[i].size);
+ /* Does this area need to be expanded? */
+ if (map_end == start) {
+ mem->map[i].size = pack_lb64(end - map_start);
+ }
+ /* Does this area need to be contracted? */
+ else if (map_start == start) {
+ mem->map[i].start = pack_lb64(end);
+ mem->map[i].size = pack_lb64(map_end - end);
+ }
+ }
+}
+
+static unsigned long lb_table_fini(struct lb_header *head, int fixup)
+{
+ struct lb_record *rec, *first_rec;
+ rec = lb_last_record(head);
+ if (head->table_entries) {
+ head->table_bytes += rec->size;
+ }
+
+ if (fixup)
+ lb_reserve_table_memory(head);
+
+ first_rec = lb_first_record(head);
+ head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
+ head->header_checksum = 0;
+ head->header_checksum = compute_ip_checksum(head, sizeof(*head));
+ printk(BIOS_DEBUG,
+ "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n",
+ head, head->table_bytes, head->table_checksum);
+ return (unsigned long)rec + rec->size;
+}
+
+static void lb_cleanup_memory_ranges(struct lb_memory *mem)
+{
+ int entries;
+ int i, j;
+ entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
+
+ /* Sort the lb memory ranges */
+ for(i = 0; i < entries; i++) {
+ uint64_t entry_start = unpack_lb64(mem->map[i].start);
+ for(j = i; j < entries; j++) {
+ uint64_t temp_start = unpack_lb64(mem->map[j].start);
+ if (temp_start < entry_start) {
+ struct lb_memory_range tmp;
+ tmp = mem->map[i];
+ mem->map[i] = mem->map[j];
+ mem->map[j] = tmp;
+ }
+ }
+ }
+
+ /* Merge adjacent entries */
+ for(i = 0; (i + 1) < entries; i++) {
+ uint64_t start, end, nstart, nend;
+ if (mem->map[i].type != mem->map[i + 1].type) {
+ continue;
+ }
+ start = unpack_lb64(mem->map[i].start);
+ end = start + unpack_lb64(mem->map[i].size);
+ nstart = unpack_lb64(mem->map[i + 1].start);
+ nend = nstart + unpack_lb64(mem->map[i + 1].size);
+ if ((start <= nstart) && (end > nstart)) {
+ if (start > nstart) {
+ start = nstart;
+ }
+ if (end < nend) {
+ end = nend;
+ }
+ /* Record the new region size */
+ mem->map[i].start = pack_lb64(start);
+ mem->map[i].size = pack_lb64(end - start);
+
+ /* Delete the entry I have merged with */
+ memmove(&mem->map[i + 1], &mem->map[i + 2],
+ ((entries - i - 2) * sizeof(mem->map[0])));
+ mem->size -= sizeof(mem->map[0]);
+ entries -= 1;
+ /* See if I can merge with the next entry as well */
+ i -= 1;
+ }
+ }
+}
+
+static void lb_remove_memory_range(struct lb_memory *mem,
+ uint64_t start, uint64_t size)
+{
+ uint64_t end;
+ int entries;
+ int i;
+
+ end = start + size;
+ entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
+
+ /* Remove a reserved area from the memory map */
+ for(i = 0; i < entries; i++) {
+ uint64_t map_start = unpack_lb64(mem->map[i].start);
+ uint64_t map_end = map_start + unpack_lb64(mem->map[i].size);
+ if ((start <= map_start) && (end >= map_end)) {
+ /* Remove the completely covered range */
+ memmove(&mem->map[i], &mem->map[i + 1],
+ ((entries - i - 1) * sizeof(mem->map[0])));
+ mem->size -= sizeof(mem->map[0]);
+ entries -= 1;
+ /* Since the index will disappear revisit what will appear here */
+ i -= 1;
+ }
+ else if ((start > map_start) && (end < map_end)) {
+ /* Split the memory range */
+ memmove(&mem->map[i + 1], &mem->map[i],
+ ((entries - i) * sizeof(mem->map[0])));
+ mem->size += sizeof(mem->map[0]);
+ entries += 1;
+ /* Update the first map entry */
+ mem->map[i].size = pack_lb64(start - map_start);
+ /* Update the second map entry */
+ mem->map[i + 1].start = pack_lb64(end);
+ mem->map[i + 1].size = pack_lb64(map_end - end);
+ /* Don't bother with this map entry again */
+ i += 1;
+ }
+ else if ((start <= map_start) && (end > map_start)) {
+ /* Shrink the start of the memory range */
+ mem->map[i].start = pack_lb64(end);
+ mem->map[i].size = pack_lb64(map_end - end);
+ }
+ else if ((start < map_end) && (start > map_start)) {
+ /* Shrink the end of the memory range */
+ mem->map[i].size = pack_lb64(start - map_start);
+ }
+ }
+}
+
+static void lb_add_memory_range(struct lb_memory *mem,
+ uint32_t type, uint64_t start, uint64_t size)
+{
+ lb_remove_memory_range(mem, start, size);
+ new_lb_memory_range(mem, type, start, size);
+ lb_cleanup_memory_ranges(mem);
+}
+
+static void lb_dump_memory_ranges(struct lb_memory *mem)
+{
+ int entries;
+ int i;
+ entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]);
+
+ printk(BIOS_DEBUG, "coreboot memory table:\n");
+ for(i = 0; i < entries; i++) {
+ uint64_t entry_start = unpack_lb64(mem->map[i].start);
+ uint64_t entry_size = unpack_lb64(mem->map[i].size);
+ const char *entry_type;
+
+ switch (mem->map[i].type) {
+ case LB_MEM_RAM: entry_type="RAM"; break;
+ case LB_MEM_RESERVED: entry_type="RESERVED"; break;
+ case LB_MEM_ACPI: entry_type="ACPI"; break;
+ case LB_MEM_NVS: entry_type="NVS"; break;
+ case LB_MEM_UNUSABLE: entry_type="UNUSABLE"; break;
+ case LB_MEM_VENDOR_RSVD: entry_type="VENDOR RESERVED"; break;
+ case LB_MEM_TABLE: entry_type="CONFIGURATION TABLES"; break;
+ default: entry_type="UNKNOWN!"; break;
+ }
+
+ printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n",
+ i, entry_start, entry_start+entry_size-1, entry_type);
+
+ }
+}
+
+
+/* Routines to extract part so the coreboot table or
+ * information from the coreboot table after we have written it.
+ * Currently get_lb_mem relies on a global we can change the
+ * implementaiton.
+ */
+static struct lb_memory *mem_ranges = 0;
+struct lb_memory *get_lb_mem(void)
+{
+ return mem_ranges;
+}
+
+static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res)
+{
+ struct lb_memory *mem = gp;
+ new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size);
+}
+
+static struct lb_memory *build_lb_mem(struct lb_header *head)
+{
+ struct lb_memory *mem;
+
+ /* Record where the lb memory ranges will live */
+ mem = lb_memory(head);
+ mem_ranges = mem;
+
+ /* Build the raw table of memory */
+ search_global_resources(
+ IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
+ build_lb_mem_range, mem);
+ lb_cleanup_memory_ranges(mem);
+ return mem;
+}
+
+static void lb_add_rsvd_range(void *gp, struct device *dev, struct resource *res)
+{
+ struct lb_memory *mem = gp;
+ lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size);
+}
+
+static void add_lb_reserved(struct lb_memory *mem)
+{
+ /* Add reserved ranges */
+ search_global_resources(
+ IORESOURCE_MEM | IORESOURCE_RESERVE, IORESOURCE_MEM | IORESOURCE_RESERVE,
+ lb_add_rsvd_range, mem);
+}
+
+unsigned long write_coreboot_table(
+ unsigned long low_table_start, unsigned long low_table_end,
+ unsigned long rom_table_start, unsigned long rom_table_end)
+{
+ struct lb_header *head;
+ struct lb_memory *mem;
+
+#if CONFIG_WRITE_HIGH_TABLES
+ printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n",
+ low_table_end);
+ head = lb_table_init(low_table_end);
+ lb_forward(head, (struct lb_header*)rom_table_end);
+
+ low_table_end = (unsigned long) lb_table_fini(head, 0);
+ printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end);
+ printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n",
+ rom_table_end);
+
+ head = lb_table_init(rom_table_end);
+ rom_table_end = (unsigned long)head;
+ printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
+#else
+ if(low_table_end > (0x1000 - sizeof(struct lb_header))) { /* after 4K */
+ /* We need to put lbtable on to [0xf0000,0x100000) */
+ head = lb_table_init(rom_table_end);
+ rom_table_end = (unsigned long)head;
+ } else {
+ head = lb_table_init(low_table_end);
+ low_table_end = (unsigned long)head;
+ }
+#endif
+
+ printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end);
+ low_table_end += 0xfff; // 4K aligned
+ low_table_end &= ~0xfff;
+ printk(BIOS_DEBUG, "0x%08lx \n", low_table_end);
+
+ /* The Linux kernel assumes this region is reserved */
+ printk(BIOS_DEBUG, "Adjust rom_table_end from 0x%08lx to ", rom_table_end);
+ rom_table_end += 0xffff; // 64K align
+ rom_table_end &= ~0xffff;
+ printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end);
+
+#if CONFIG_USE_OPTION_TABLE
+ {
+ struct cmos_option_table *option_table = cbfs_find_file("cmos_layout.bin", 0x1aa);
+ if (option_table) {
+ struct lb_record *rec_dest = lb_new_record(head);
+ /* Copy the option config table, it's already a lb_record... */
+ memcpy(rec_dest, option_table, option_table->size);
+ /* Create cmos checksum entry in coreboot table */
+ lb_cmos_checksum(head);
+ } else {
+ printk(BIOS_ERR, "cmos_layout.bin could not be found!\n");
+ }
+ }
+#endif
+ /* Record where RAM is located */
+ mem = build_lb_mem(head);
+
+ /* Record the mptable and the the lb_table (This will be adjusted later) */
+ lb_add_memory_range(mem, LB_MEM_TABLE,
+ low_table_start, low_table_end - low_table_start);
+
+ /* Record the pirq table, acpi tables, and maybe the mptable */
+ lb_add_memory_range(mem, LB_MEM_TABLE,
+ rom_table_start, rom_table_end-rom_table_start);
+
+#if CONFIG_WRITE_HIGH_TABLES
+ printk(BIOS_DEBUG, "Adding high table area\n");
+ // should this be LB_MEM_ACPI?
+ lb_add_memory_range(mem, LB_MEM_TABLE,
+ high_tables_base, high_tables_size);
+#endif
+
+ /* Add reserved regions */
+ add_lb_reserved(mem);
+
+ lb_dump_memory_ranges(mem);
+
+ /* Note:
+ * I assume that there is always memory at immediately after
+ * the low_table_end. This means that after I setup the coreboot table.
+ * I can trivially fixup the reserved memory ranges to hold the correct
+ * size of the coreboot table.
+ */
+
+ /* Record our motherboard */
+ lb_mainboard(head);
+ /* Record the serial port, if present */
+ lb_serial(head);
+ /* Record our console setup */
+ lb_console(head);
+ /* Record our various random string information */
+ lb_strings(head);
+ /* Record our framebuffer */
+ lb_framebuffer(head);
+
+#if CONFIG_CHROMEOS
+ /* Record our GPIO settings (ChromeOS specific) */
+ lb_gpios(head);
+
+ /* pass along the VDAT buffer adress */
+ lb_vdat(head);
+
+ /* pass along VBNV offsets in CMOS */
+ lb_vbnv(head);
+#endif
+ add_cbmem_pointers(head);
+
+ /* Remember where my valid memory ranges are */
+ return lb_table_fini(head, 1);
+
+}
diff --git a/src/arch/armv7/boot/multiboot.c b/src/arch/armv7/boot/multiboot.c
new file mode 100644
index 0000000000..4059f2736b
--- /dev/null
+++ b/src/arch/armv7/boot/multiboot.c
@@ -0,0 +1,77 @@
+/*
+ * support for Multiboot payloads
+ *
+ * Copyright (C) 2008 Robert Millan
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <cpu/x86/multiboot.h>
+#include <string.h>
+#include <device/resource.h>
+#include <console/console.h>
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+
+struct multiboot_info *mbi = NULL;
+
+unsigned long write_multiboot_info(unsigned long rom_table_end)
+{
+ static struct multiboot_mmap_entry *mb_mem;
+ struct lb_memory* coreboot_table;
+ int entries;
+ int i;
+
+ mbi = (struct multiboot_info *)rom_table_end;
+
+ memset(mbi, 0, sizeof(*mbi));
+ rom_table_end += sizeof(*mbi);
+
+ mbi->mmap_addr = (u32) rom_table_end;
+ mb_mem = (struct multiboot_mmap_entry *)rom_table_end;
+
+ /* copy regions from coreboot tables */
+ coreboot_table = get_lb_mem();
+ entries = (coreboot_table->size - sizeof(*coreboot_table))/sizeof(coreboot_table->map[0]);
+
+ if (coreboot_table == NULL || entries < 1) {
+ printk(BIOS_INFO, "%s: Cannot find coreboot table.\n", __func__);
+ return (unsigned long) mb_mem;
+ }
+
+ for (i = 0; i < entries; i++) {
+ uint64_t entry_start = unpack_lb64(coreboot_table->map[i].start);
+ uint64_t entry_size = unpack_lb64(coreboot_table->map[i].size);
+ mb_mem->addr = entry_start;
+ mb_mem->len = entry_size;
+ switch (coreboot_table->map[i].type) {
+ case LB_MEM_RAM:
+ mb_mem->type = MULTIBOOT_MEMORY_AVAILABLE;
+ break;
+ default: // anything other than usable RAM
+ mb_mem->type = MULTIBOOT_MEMORY_RESERVED;
+ break;
+ }
+ mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size);
+ mb_mem++;
+ }
+
+ mbi->mmap_length = ((u32) mb_mem) - mbi->mmap_addr;
+ mbi->flags |= MB_INFO_MEM_MAP;
+
+ printk(BIOS_INFO, "Multiboot Information structure has been written.\n");
+
+ return (unsigned long)mb_mem;
+}
diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c
new file mode 100644
index 0000000000..07c56354c8
--- /dev/null
+++ b/src/arch/armv7/boot/tables.c
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2005 Steve Magnani
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+#include <string.h>
+#include <cbmem.h>
+#include <lib.h>
+
+uint64_t high_tables_base = 0;
+uint64_t high_tables_size;
+
+void cbmem_arch_init(void)
+{
+}
+
+struct lb_memory *write_tables(void)
+{
+ unsigned long low_table_start, low_table_end;
+ unsigned long rom_table_start, rom_table_end;
+
+ /* Even if high tables are configured, some tables are copied both to
+ * the low and the high area, so payloads and OSes don't need to know
+ * about the high tables.
+ */
+ unsigned long high_table_pointer;
+
+ if (!high_tables_base) {
+ printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n");
+ // Are there any boards without?
+ // Stepan thinks we should die() here!
+ }
+
+ printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base);
+
+ rom_table_start = 0xf0000;
+ rom_table_end = 0xf0000;
+
+ /* Start low addr at 0x500, so we don't run into conflicts with the BDA
+ * in case our data structures grow beyound 0x400. Only multiboot, GDT
+ * and the coreboot table use low_tables.
+ */
+ low_table_start = 0;
+ low_table_end = 0x500;
+
+#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+ post_code(0x9d);
+
+ high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE);
+
+ if (high_table_pointer) {
+ unsigned long new_high_table_pointer;
+
+ /* Also put a forwarder entry into 0-4K */
+ new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end,
+ high_tables_base, high_table_pointer);
+
+ if (new_high_table_pointer > (high_table_pointer +
+ MAX_COREBOOT_TABLE_SIZE))
+ printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n",
+ __func__, new_high_table_pointer -
+ high_table_pointer);
+
+ printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
+ new_high_table_pointer - high_table_pointer);
+ } else {
+ /* The coreboot table must be in 0-4K or 960K-1M */
+ rom_table_end = write_coreboot_table(
+ low_table_start, low_table_end,
+ rom_table_start, rom_table_end);
+ }
+
+ post_code(0x9e);
+
+ // Remove before sending upstream
+ cbmem_list();
+
+ return get_lb_mem();
+}
diff --git a/src/arch/armv7/boot/wakeup.S b/src/arch/armv7/boot/wakeup.S
new file mode 100644
index 0000000000..8ae337ca5d
--- /dev/null
+++ b/src/arch/armv7/boot/wakeup.S
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define WAKEUP_BASE 0x600
+#define RELOCATED(x) (x - __wakeup + WAKEUP_BASE)
+
+/* CR0 bits */
+#define PE (1 << 0)
+
+ .code32
+ .globl __wakeup
+__wakeup:
+ /* First prepare the jmp to the resume vector */
+ mov 0x4(%esp), %eax /* vector */
+ /* last 4 bits of linear addr are taken as offset */
+ andw $0x0f, %ax
+ movw %ax, (__wakeup_offset)
+ mov 0x4(%esp), %eax
+ /* the rest is taken as segment */
+ shr $4, %eax
+ movw %ax, (__wakeup_segment)
+
+ /* Then overwrite coreboot with our backed up memory */
+ cld
+ movl 8(%esp), %esi
+ movl 12(%esp), %edi
+ movl 16(%esp), %ecx
+ shrl $2, %ecx
+ rep movsl
+
+ /* Activate the right segment descriptor real mode. */
+ ljmp $0x28, $RELOCATED(1f)
+1:
+.code16
+ /* 16 bit code from here on... */
+
+ /* Load the segment registers w/ properly configured
+ * segment descriptors. They will retain these
+ * configurations (limits, writability, etc.) once
+ * protected mode is turned off.
+ */
+ mov $0x30, %ax
+ mov %ax, %ds
+ mov %ax, %es
+ mov %ax, %fs
+ mov %ax, %gs
+ mov %ax, %ss
+
+ /* Turn off protection */
+ movl %cr0, %eax
+ andl $~PE, %eax
+ movl %eax, %cr0
+
+ /* Now really going into real mode */
+ ljmp $0, $RELOCATED(1f)
+1:
+ movw $0x0, %ax
+ movw %ax, %ds
+ movw %ax, %es
+ movw %ax, %ss
+ movw %ax, %fs
+ movw %ax, %gs
+
+ /* This is a FAR JMP to the OS waking vector. The C code changed
+ * the address to be correct.
+ */
+ .byte 0xea
+
+__wakeup_offset = RELOCATED(.)
+ .word 0x0000
+
+__wakeup_segment = RELOCATED(.)
+ .word 0x0000
+
+ .globl __wakeup_size
+__wakeup_size = ( . - __wakeup)
+