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authorRonald G. Minnich <rminnich@gmail.com>2013-02-20 15:46:46 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-02-25 18:50:00 +0100
commit3faa2c77ed9103839002d1092424676790f07017 (patch)
tree9744ab04553e7ed3be1714fd4eb765d582a950c1 /src/arch/armv7/boot
parent5f20b3522212f58b5e6858ff7028fb5a8e0879f5 (diff)
downloadcoreboot-3faa2c77ed9103839002d1092424676790f07017.tar.xz
google/snow: enable GPIO entries and CHROMEOS in building
These were not separable or it would have been two CLs. Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. Add a chromeos.c file for snow, needed to build. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2467 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/armv7/boot')
-rw-r--r--src/arch/armv7/boot/coreboot_table.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c
index 2810a5e990..55610acd7d 100644
--- a/src/arch/armv7/boot/coreboot_table.c
+++ b/src/arch/armv7/boot/coreboot_table.c
@@ -23,7 +23,6 @@
#include <console/console.h>
#include <ip_checksum.h>
#include <boot/tables.h>
-#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
#include <string.h>
#include <version.h>
@@ -35,7 +34,7 @@
#include <option_table.h>
#endif
#if CONFIG_CHROMEOS
-#include <arch/acpi.h>
+//#include <arch/acpi.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -183,11 +182,10 @@ static void lb_gpios(struct lb_header *header)
struct lb_gpios *gpios;
gpios = (struct lb_gpios *)lb_new_record(header);
gpios->tag = LB_TAG_GPIO;
- gpios->size = sizeof(*gpios);
- gpios->count = 0;
fill_lb_gpios(gpios);
}
+#if 0
static void lb_vdat(struct lb_header *header)
{
struct lb_vdat* vdat;
@@ -209,6 +207,7 @@ static void lb_vbnv(struct lb_header *header)
vbnv->vbnv_size = CONFIG_VBNV_SIZE;
}
#endif
+#endif
static void add_cbmem_pointers(struct lb_header *header)
{
@@ -656,12 +655,11 @@ unsigned long write_coreboot_table(
lb_strings(head);
/* Record our framebuffer */
lb_framebuffer(head);
-
-#if 0
#if CONFIG_CHROMEOS
/* Record our GPIO settings (ChromeOS specific) */
lb_gpios(head);
+#if 0
/* pass along the VDAT buffer adress */
lb_vdat(head);