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authorMartin Roth <martin.roth@se-eng.com>2013-07-08 16:22:10 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 20:16:25 +0200
commit7b5f8ef2eab7f1211888ae420d76176f49721601 (patch)
tree82ad463c16b6f2e12499e606ae9e27a507fffd7b /src/arch/armv7/include
parentfb370130f6618d53f506566737f7394ee1417c55 (diff)
downloadcoreboot-7b5f8ef2eab7f1211888ae420d76176f49721601.tar.xz
arch: Fix spelling
Change-Id: Ifea10f0180c0c4b684030a168402a95fadf1a9db Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3727 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/armv7/include')
-rw-r--r--src/arch/armv7/include/armv7.h2
-rw-r--r--src/arch/armv7/include/assembler.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/armv7/include/armv7.h b/src/arch/armv7/include/armv7.h
index dc111c17ee..147323457a 100644
--- a/src/arch/armv7/include/armv7.h
+++ b/src/arch/armv7/include/armv7.h
@@ -59,7 +59,7 @@
/*
* CP15 Barrier instructions
* Please note that we have separate barrier instructions in ARMv7
- * However, we use the CP15 based instructtions because we use
+ * However, we use the CP15 based instructions because we use
* -march=armv5 in U-Boot
*/
#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
diff --git a/src/arch/armv7/include/assembler.h b/src/arch/armv7/include/assembler.h
index 5e4789b145..7acf0f4a9a 100644
--- a/src/arch/armv7/include/assembler.h
+++ b/src/arch/armv7/include/assembler.h
@@ -55,6 +55,6 @@
#endif
/*
- * Cache alligned
+ * Cache aligned
*/
#define CALGN(code...) code