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authorDavid Hendricks <dhendrix@chromium.org>2013-03-28 19:04:14 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-03-29 07:48:00 +0100
commit8234874fbc10d71f620a2814a1faaed3b097db6c (patch)
tree505268316770eae4f52633af10890b2526b85c55 /src/arch/armv7/include
parentfa244a6c09611833e78641604c96c1ea98b3bf6f (diff)
downloadcoreboot-8234874fbc10d71f620a2814a1faaed3b097db6c.tar.xz
armv7: add functions for reading/writing L2CTLR
This adds simple accessor functions for reading/writing L2CTLR. Change-Id: I2768d00d5bb2c43e84741ccead81e529dac9254d Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2948 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/armv7/include')
-rw-r--r--src/arch/armv7/include/arch/cache.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
index f074a3b158..3e0ff2e1ce 100644
--- a/src/arch/armv7/include/arch/cache.h
+++ b/src/arch/armv7/include/arch/cache.h
@@ -219,6 +219,25 @@ static inline void write_csselr(uint32_t val)
isb(); /* ISB to sync the change to CCSIDR */
}
+/* read L2 control register (L2CTLR) */
+static inline unsigned int read_l2ctlr(void)
+{
+ unsigned int val = 0;
+ asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
+ return val;
+}
+
+/* write L2 control register (L2CTLR) */
+static inline void write_l2ctlr(uint32_t val)
+{
+ /*
+ * Note: L2CTLR can only be written when the L2 memory system
+ * is idle, ie before the MMU is enabled.
+ */
+ asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" );
+ isb();
+}
+
/* read system control register (SCTLR) */
static inline unsigned int read_sctlr(void)
{