diff options
author | David Hendricks <dhendrix@chromium.org> | 2013-03-14 15:24:57 -0700 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-19 22:23:45 +0100 |
commit | bba809042191bd3e421bdec0b974ce697e85bcba (patch) | |
tree | 26856e25145a103b032afa19d35345e36b03cd7e /src/arch/armv7/lib/cache_v7.c | |
parent | f7c6d489ae28af611811515c1df96cfb10c79e9f (diff) | |
download | coreboot-bba809042191bd3e421bdec0b974ce697e85bcba.tar.xz |
armv7/exynos/snow: new cache maintenance API
This adds a new API for cache maintenance operations. The idea is
to be more explicit about operations that are going on so it's easier
to manage branch predictor, cache, and TLB cleans and invalidations.
Also, this adds some operations that were missing but required early
on, such as branch predictor invalidation. Instruction and sync
barriers were wrong earlier as well since the imported API assumed
we compield with -march=armv5 (which we don't) and was missing
wrappers for the native ARMv7 ISB/DSB/DMB instructions.
For now, this is a start and it gives us something we can easily use
in libpayload for doing things like cleaning and invalidating dcache
when doing DMA transfers.
TODO:
- Set cache policy explicitly before re-enabling. Right now it's left
at default.
- Finish deprecating old cache maintenance API.
- We do an extra icache/dcache flush when going from bootblock to
romstage.
Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2729
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/armv7/lib/cache_v7.c')
-rw-r--r-- | src/arch/armv7/lib/cache_v7.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/armv7/lib/cache_v7.c b/src/arch/armv7/lib/cache_v7.c index 31072c7c50..1764351115 100644 --- a/src/arch/armv7/lib/cache_v7.c +++ b/src/arch/armv7/lib/cache_v7.c @@ -226,7 +226,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* Invalidate TLB */ -static void v7_inval_tlb(void) +void v7_inval_tlb(void) { /* Invalidate entire unified TLB */ asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); |