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authorGabe Black <gabeblack@google.com>2013-06-14 15:53:23 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 21:49:45 +0200
commit001056f560dfec46aa98659f318819cce7098e5b (patch)
treeaf939cc185e537070c151df96417a65fd89e5aed /src/arch/armv7
parentfbb11cf97937c345a42a45737fc7a95ee7ee3e7e (diff)
downloadcoreboot-001056f560dfec46aa98659f318819cce7098e5b.tar.xz
ARM: Tell the linker memset and memcpy are functions.
The memset and memcpy functions are assembled as ARM code, likely because that's the default of the assembler. Without special annotation, the assembler and linker don't know that those symbols are functions which need special handling so that ARM/thumb issues are handled properly. This change adds that annotation which gets those functions working in Coreboot which is compiled as thumb. Libpayload and depthcharge are compiled as ARM so they don't *need* the annotation since it just works out in ARM mode, but it's the safe thing to do in case we change that in the future. We should explicitly select ARM vs. thumb when assembling assembly files to be consistent across builds and toolchains. Change-Id: I814b137064cf46ae9e2744ff6c223b695dc1ef01 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3672 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/armv7')
-rw-r--r--src/arch/armv7/memcpy.S1
-rw-r--r--src/arch/armv7/memset.S1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/armv7/memcpy.S b/src/arch/armv7/memcpy.S
index f04113f279..921fc2a6bc 100644
--- a/src/arch/armv7/memcpy.S
+++ b/src/arch/armv7/memcpy.S
@@ -57,6 +57,7 @@
/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
+.type memcpy, function
.globl memcpy
memcpy:
diff --git a/src/arch/armv7/memset.S b/src/arch/armv7/memset.S
index 3ea2721227..a3cc9477f8 100644
--- a/src/arch/armv7/memset.S
+++ b/src/arch/armv7/memset.S
@@ -27,6 +27,7 @@
* memset again.
*/
+.type memset, function
.globl memset
memset:
ands r3, r0, #3 @ 1 unaligned?