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authorDavid Hendricks <dhendrix@chromium.org>2013-02-10 15:50:20 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-02-11 02:31:34 +0100
commit5d994634a268d29b61c98f40f4793334078509c4 (patch)
tree16888af3c0249188b82947d62a68e81a1c27abf2 /src/arch/armv7
parenta40435af84c5cd2175b842ff0cbd9d1e909c2ce6 (diff)
downloadcoreboot-5d994634a268d29b61c98f40f4793334078509c4.tar.xz
armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply the same way on ARM platforms. On x86 they refer to the low memory region where coreboot tables reside. However on ARM we don't have such a region which is architecturally defined. So instead we'll use the CPU-defined DRAM base address and the mainboard-defined DRAM size. This also has the pleasant side-effect of fixing the coreboot tables to not clobber ramstage code... Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2351 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/armv7')
-rw-r--r--src/arch/armv7/coreboot_ram.ld7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld
index c69499c362..0644e3669d 100644
--- a/src/arch/armv7/coreboot_ram.ld
+++ b/src/arch/armv7/coreboot_ram.ld
@@ -26,7 +26,7 @@ ENTRY(_start)
SECTIONS
{
- . = CONFIG_RAMBASE;
+ . = CONFIG_SYS_SDRAM_BASE;
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
@@ -123,11 +123,6 @@ SECTIONS
_ram_seg = _text;
_eram_seg = _eheap;
- /* CONFIG_RAMTOP is the upper address of cached memory (among other
- * things). We must not exceed beyond that address, there be dragons.
- */
- _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
-
/* Discard the sections we don't need/want */
/DISCARD/ : {