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| author | David Hendricks <dhendrix@chromium.org> | 2013-08-06 17:32:41 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 22:45:28 +0100 |
| commit | 36e62c2516ef46e726af79da3d14dfa416e468ab (patch) | |
| tree | da83cdb30a4884c8b3ac9c7fd0322ca5267afc60 /src/arch/armv7 | |
| parent | 49832975c3c0ea152873f868d829f6ed819bb915 (diff) | |
| download | coreboot-36e62c2516ef46e726af79da3d14dfa416e468ab.tar.xz | |
armv7: add wrappers to read/write L2ACTLR
This adds inline wrappers to read the L2 cache auxiliary control
register (L2ACTLR).
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f
Reviewed-on: https://gerrit.chromium.org/gerrit/64861
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4437
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/arch/armv7')
| -rw-r--r-- | src/arch/armv7/include/arch/cache.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 5166af3f9b..8a14ff9388 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -246,6 +246,21 @@ static inline void write_l2ctlr(uint32_t val) isb(); } +/* read L2 Auxiliary Control Register (L2ACTLR) */ +static inline uint32_t read_l2actlr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); + return val; +} + +/* write L2 Auxiliary Control Register (L2ACTLR) */ +static inline void write_l2actlr(uint32_t val) +{ + asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" ); + isb(); +} + /* read system control register (SCTLR) */ static inline uint32_t read_sctlr(void) { |