- A new test case for romcc

- Minor romcc fixes
- In smbus_wail_until_done a romcc glitch with || in romcc where it likes
  to run out of registers.  Use | to be explicit that I don't need the short
  circuiting behavior.
- Remove unused #defines from coherent_ht.c
- Update the test in auto.c to 512M
- Add definition of log2 to romcc_io.h
- Implement SPD memory sizing in raminit.c
- Reduce the number of memory devices back 2 to for the SOLO board.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 12 insertions, 0 deletions

diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h
index 7d3d50e39c..d67b3b60d6 100644
--- a/src/arch/i386/include/arch/romcc_io.h
+++ b/src/arch/i386/include/arch/romcc_io.h
@@ -35,6 +35,18 @@ static void hlt(void)
 	__builtin_hlt();
 }
 
+int log2(int value)
+{
+	/* __builtin_bsr is a exactly equivalent to the x86 machine
+	 * instruction with the exception that it returns -1  
+	 * when the value presented to it is zero.
+	 * Otherwise __builtin_bsr returns the zero based index of
+	 * the highest bit set.
+	 */
+	return __builtin_bsr(value);
+}
+
+
 typedef __builtin_msr_t msr_t;
 
 static msr_t rdmsr(unsigned long index)