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authorLi-Ta Lo <ollie@lanl.gov>2004-03-26 18:34:48 +0000
committerLi-Ta Lo <ollie@lanl.gov>2004-03-26 18:34:48 +0000
commit8cb91dc9f832cb3df7aa74b4990a297d48133cfb (patch)
tree3803e1913525e393721a35fe246c40c2a55be0b0 /src/arch/i386/lib
parent23e2e18960d5ffed4bc8bb082f1ef8e471307657 (diff)
downloadcoreboot-8cb91dc9f832cb3df7aa74b4990a297d48133cfb.tar.xz
speed up ecc clear by enable MTRR/Cache first.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch/i386/lib')
-rw-r--r--src/arch/i386/lib/cpu.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/i386/lib/cpu.c b/src/arch/i386/lib/cpu.c
index f459f3a853..9af2bfb8c0 100644
--- a/src/arch/i386/lib/cpu.c
+++ b/src/arch/i386/lib/cpu.c
@@ -126,15 +126,15 @@ unsigned long cpu_initialize(struct mem_range *mem)
unsigned long processor_id = this_processors_id();
printk_notice("Initializing CPU #%d\n", processor_id);
- /* some cpus need a fixup done. This is the hook for doing that. */
- cpufixup(mem);
-
/* Turn on caching if we haven't already */
cache_on(mem);
display_cpuid();
mtrr_check();
+ /* some cpus need a fixup done. This is the hook for doing that. */
+ cpufixup(mem);
+
#if 0
/* now that everything is really up, enable the l2 cache if desired.
* The enable can wait until this point, because linuxbios and it's
@@ -142,6 +142,7 @@ unsigned long cpu_initialize(struct mem_range *mem)
*/
configure_l2_cache();
#endif
+
interrupts_on();
processor_id = this_processors_id();
printk_info("CPU #%d Initialized\n", processor_id);