diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-13 22:07:15 +0000 |
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committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-13 22:07:15 +0000 |
commit | 5c503927f482cc167ebe245ac6d4a394179ea6e2 (patch) | |
tree | 9b53ebd38ebb51434f0ebacd117b85357d0a40fb /src/arch/i386/llshell/ramtest.inc | |
parent | 53c7276bd1a18160f022c468b7ce021c5386577c (diff) | |
download | coreboot-5c503927f482cc167ebe245ac6d4a394179ea6e2.tar.xz |
Fix llshell
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch/i386/llshell/ramtest.inc')
-rw-r--r-- | src/arch/i386/llshell/ramtest.inc | 125 |
1 files changed, 125 insertions, 0 deletions
diff --git a/src/arch/i386/llshell/ramtest.inc b/src/arch/i386/llshell/ramtest.inc new file mode 100644 index 0000000000..dfe06adf71 --- /dev/null +++ b/src/arch/i386/llshell/ramtest.inc @@ -0,0 +1,125 @@ + /* + * This is much more of a "Is my SDRAM properly configured?" + * test than a "Is my SDRAM faulty?" test. Not all bits + * are tested. -Tyson + */ + + jmp rt_skip +#define RAMTEST 1 +#if RAMTEST + .section ".rom.data" + +rt_test: .string "Testing SDRAM : " +rt_fill: .string "SDRAM fill:\r\n" +rt_verify: .string "SDRAM verify:\r\n" +rt_toomany: .string "Too many errors.\r\n" +rt_done: .string "Done.\r\n" + .previous +#endif + +ramtest: +#if RAMTEST + mov %eax, %esi + mov %ebx, %edi + mov %esp, %ebp + + CONSOLE_INFO_TX_STRING($rt_test) + CONSOLE_INFO_TX_HEX32(%esi) + CONSOLE_INFO_TX_CHAR($'-') + CONSOLE_INFO_TX_HEX32(%edi) + CONSOLE_INFO_TX_CHAR($'\r') + CONSOLE_INFO_TX_CHAR($'\n') + + /* ============== Fill ram block ==== */ + + CONSOLE_INFO_TX_STRING($rt_fill) + + mov %esi, %ebx +1: + cmp $0, %bx + jne 2f + + /* Display address being filled */ + /* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */ + + CONSOLE_INFO_TX_HEX32(%ebx) + CONSOLE_INFO_TX_CHAR($'\r') +2: +#if i786 + /* Use a non temporal store to go faster and + * to bypass the cache. + */ + movnti %ebx, (%ebx) +#else + mov %ebx, (%ebx) +#endif + add $4, %ebx + cmp %edi, %ebx + jl 1b + + /* Display final address */ + + CONSOLE_INFO_TX_HEX32(%edi) + CONSOLE_INFO_TX_CHAR($'\r') + CONSOLE_INFO_TX_CHAR($'\n') + + /* ========= Verify ram block ========== */ + + CONSOLE_INFO_TX_STRING($rt_verify) + mov %esi, %ebx + +1: + cmp $0, %bx + jne 2f + + /* Display address being tested */ + + CONSOLE_INFO_TX_HEX32(%ebx) + CONSOLE_INFO_TX_CHAR($'\r') +2: + cmp %ebx, (%ebx) + jne 4f +3: + add $4, %ebx + cmp %edi, %ebx + jl 1b + + /* Display final address */ + CONSOLE_INFO_TX_HEX32(%edi) + CONSOLE_INFO_TX_CHAR($'\r') + CONSOLE_INFO_TX_CHAR($'\n') + jmp 6f + +4: + /* Display address with error */ + + CONSOLE_INFO_TX_HEX32(%ebx) + CONSOLE_INFO_TX_CHAR($':') + + /* Display data in address with error */ + + /* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */ + + mov %ebx, %esi + mov 0(%ebx), %eax + CONSOLE_INFO_TX_HEX32(%eax) + mov %esi, %ebx + + CONSOLE_INFO_TX_CHAR($'\r') + CONSOLE_INFO_TX_CHAR($'\n') + sub $1, %ecx + jz 5f + jmp 3b +5: + CONSOLE_INFO_TX_STRING($rt_toomany) + intel_chip_post_macro(0xf1) + jmp .Lhlt + +6: + CONSOLE_INFO_TX_STRING($rt_done) + mov %ebp, %esp + +#endif + RETSP + +rt_skip: |