printk_foo -> printk(BIOS_FOO, ...)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 16 insertions, 16 deletions

diff --git a/src/arch/i386/smp/ioapic.c b/src/arch/i386/smp/ioapic.c
index 630463e63d..efc2ac52fc 100644
--- a/src/arch/i386/smp/ioapic.c
+++ b/src/arch/i386/smp/ioapic.c
@@ -40,13 +40,13 @@ void clear_ioapic(u32 ioapic_base)
 	u32 low, high;
 	u32 i, ioapic_interrupts;
 
-	printk_debug("IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); 
+	printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); 
 
 	/* Read the available number of interrupts */
 	ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
 	if (!ioapic_interrupts || ioapic_interrupts == 0xff)
 		ioapic_interrupts = 24;
-	printk_debug("IOAPIC: %d interrupts\n", ioapic_interrupts); 
+	printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); 
 
 	low = DISABLED;
 	high = NONE;
@@ -55,11 +55,11 @@ void clear_ioapic(u32 ioapic_base)
 		io_apic_write(ioapic_base, i * 2 + 0x10, low);
 		io_apic_write(ioapic_base, i * 2 + 0x11, high);
 
-		printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+		printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
 	}
 
 	if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
-		printk_warning("IO APIC not responding.\n");
+		printk(BIOS_WARNING, "IO APIC not responding.\n");
 		return;
 	}
 }
@@ -70,12 +70,12 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 	u32 low, high;
 	u32 i, ioapic_interrupts;
 
-	printk_debug("IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); 
-	printk_debug("IOAPIC: Bootstrap Processor Local APIC = %02x\n",
+	printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); 
+	printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n",
 			bsp_lapicid);
 
 	if (ioapic_id) {
-		printk_debug("IOAPIC: ID = 0x%02x\n", ioapic_id); 
+		printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); 
 		/* Set IOAPIC ID if it has been specified */
 		io_apic_write(ioapic_base, 0x00, 
 			(io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | 
@@ -86,7 +86,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 	ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
 	if (!ioapic_interrupts || ioapic_interrupts == 0xff)
 		ioapic_interrupts = 24;
-	printk_debug("IOAPIC: %d interrupts\n", ioapic_interrupts); 
+	printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); 
 
 
 // XXX this decision should probably be made elsewhere, and
@@ -101,11 +101,11 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 	/* For the Pentium 4 and above APICs deliver their interrupts
 	 * on the front side bus, enable that.
 	 */
-	printk_debug("IOAPIC: Enabling interrupts on FSB\n"); 
+	printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); 
 	io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0));
 #endif
 #ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
-	printk_debug("IOAPIC: Enabling interrupts on APIC serial bus\n"); 
+	printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); 
 	io_apic_write(ioapic_base, 0x03, 0);
 #endif
 
@@ -117,11 +117,11 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 	io_apic_write(ioapic_base, 0x11, high);
 
 	if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
-		printk_warning("IO APIC not responding.\n");
+		printk(BIOS_WARNING, "IO APIC not responding.\n");
 		return;
 	}
 
-	printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low);
+	printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low);
 
 	low = DISABLED;
 	high = NONE;
@@ -130,6 +130,6 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 		io_apic_write(ioapic_base, i * 2 + 0x10, low);
 		io_apic_write(ioapic_base, i * 2 + 0x11, high);
 
-		printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+		printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
 	}
 }
diff --git a/src/arch/i386/smp/mpspec.c b/src/arch/i386/smp/mpspec.c
index 302f97ae90..1beba873cc 100644
--- a/src/arch/i386/smp/mpspec.c
+++ b/src/arch/i386/smp/mpspec.c
@@ -177,7 +177,7 @@ void smp_write_intsrc(struct mp_config_table *mc,
 	mpc->mpc_dstirq = dstirq;
 	smp_add_mpc_entry(mc, sizeof(*mpc));
 #ifdef DEBUG_MPTABLE
-	printk_debug("add intsrc srcbus 0x%x srcbusirq 0x%x, dstapic 0x%x, dstirq 0x%x\n",
+	printk(BIOS_DEBUG, "add intsrc srcbus 0x%x srcbusirq 0x%x, dstapic 0x%x, dstirq 0x%x\n",
 				srcbus, srcbusirq, dstapic, dstirq);
 	hexdump(__func__, mpc, sizeof(*mpc));
 #endif
@@ -215,7 +215,7 @@ void smp_write_intsrc_pci_bridge(struct mp_config_table *mc,
 
 			if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) {
 				/* pci device */
-				printk_debug("route irq: %s\n", dev_path(child));
+				printk(BIOS_DEBUG, "route irq: %s\n", dev_path(child));
 				for (i = 0; i < 4; i++)
 					smp_write_intsrc(mc, irqtype, irqflag, srcbus, (slot<<2)|i, dstapic, dstirq_x[i]);
 				goto next;
@@ -225,7 +225,7 @@ void smp_write_intsrc_pci_bridge(struct mp_config_table *mc,
 			case PCI_CLASS_BRIDGE_PCI:
 			case PCI_CLASS_BRIDGE_PCMCIA:
 			case PCI_CLASS_BRIDGE_CARDBUS:
-				printk_debug("route irq bridge: %s\n", dev_path(child));
+				printk(BIOS_DEBUG, "route irq bridge: %s\n", dev_path(child));
 				smp_write_intsrc_pci_bridge(mc, irqtype, irqflag, child, dstapic, dstirq_x);
 			}