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authorIonela Voinescu <ionela.voinescu@imgtec.com>2014-12-01 18:31:48 +0000
committerPatrick Georgi <pgeorgi@google.com>2015-04-13 20:25:21 +0200
commit8fa8f4bdc341d3249aec5fda87f80417cb8917b3 (patch)
treeffd3e852235ffaa45587a36a3bbd57c3b8088dee /src/arch/mips/cache.c
parent49efaf260f2289322110dcf21900146046439d37 (diff)
downloadcoreboot-8fa8f4bdc341d3249aec5fda87f80417cb8917b3.tar.xz
arch/mips: provide proper cache primitives
This provides the opportunity to remove the kludge of disabling caches altogether in the bootblock. [pg: originally, this commit also provided automatic cache management after loading stages, ie. flush dcache, so code ends up in icache. This is done differently in upstream, so it's left out here] BUG=chrome-os-partner:34127, chrome-os-partner:31438 TEST=with this fix romstage, ramstage and payload are executed properly BRANCH=none Change-Id: I568c68d02b2cd9c1c2c9c1495ba3343c82509ccc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 95ab0f159cabf21fc100f371d451211e7d113761 Original-Change-Id: Iaf90b052073dd355ab9114e8dba9f5ef76188c94 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/232410 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9618 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/mips/cache.c')
-rw-r--r--src/arch/mips/cache.c112
1 files changed, 112 insertions, 0 deletions
diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c
new file mode 100644
index 0000000000..209349539d
--- /dev/null
+++ b/src/arch/mips/cache.c
@@ -0,0 +1,112 @@
+
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/cache.h>
+#include <symbols.h>
+
+/* Cache operations */
+
+/*
+ * __get_line_size:
+ * Read config register
+ * Isolate instruction cache line size
+ * Interpret value as per MIPS manual: 2 << value
+ * Return cache line size
+ */
+#define __get_line_size(cfg_no, cfg_sel, lshift, nobits) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ ".set mips32\n\t" \
+ "mfc0 $t5, "#cfg_no"," #cfg_sel"\n\t" \
+ ".set mips0\n\t" \
+ "ext $t6, $t5," #lshift"," #nobits"\n\t" \
+ "li $t7, 2\n\t" \
+ "sllv %0, $t7, $t6\n\t" \
+ ".set pop\n\t" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+/* clear_L2tag: clear L23Tag register */
+#define clear_L2tag() \
+({ \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ ".set mips32\n\t" \
+ "mtc0 $zero, $28, 4\n\t" \
+ ".set mips0\n\t" \
+ ".set pop\n\t" \
+ ); \
+})
+
+/* cache_op: issues cache operation for specified address */
+#define cache_op(op, addr) \
+({ \
+ __asm__ __volatile__( \
+ ".set push\n\t" \
+ ".set noreorder\n\t" \
+ ".set mips32\n\t" \
+ "cache %0, %1\n\t" \
+ ".set mips0\n\t" \
+ ".set pop\n\t" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr))); \
+})
+
+void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation)
+{
+ u32 line_size, line_mask;
+ uintptr_t end;
+
+ line_size = get_icache_line();
+ line_mask = ~(line_size-1);
+ end = (start + (line_size - 1) + size) & line_mask;
+ start &= line_mask;
+ if ((operation & L2CACHE) == L2CACHE)
+ clear_L2tag();
+ while (start < end) {
+ switch (operation) {
+ case CACHE_CODE(ICACHE, WB_INVD):
+ cache_op(CACHE_CODE(ICACHE, WB_INVD), start);
+ break;
+ case CACHE_CODE(DCACHE, WB_INVD):
+ cache_op(CACHE_CODE(DCACHE, WB_INVD), start);
+ break;
+ case CACHE_CODE(L2CACHE, WB_INVD):
+ cache_op(CACHE_CODE(L2CACHE, WB_INVD), start);
+ break;
+ default:
+ return;
+ }
+ start += line_size;
+ }
+ asm("sync");
+}
+
+void cache_invalidate_all(uintptr_t start, size_t size)
+{
+ perform_cache_operation(start, size, CACHE_CODE(ICACHE, WB_INVD));
+ perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD));
+ perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD));
+
+}