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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2014-12-01 18:31:48 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-13 20:25:21 +0200 |
| commit | 8fa8f4bdc341d3249aec5fda87f80417cb8917b3 (patch) | |
| tree | ffd3e852235ffaa45587a36a3bbd57c3b8088dee /src/arch/mips/include | |
| parent | 49efaf260f2289322110dcf21900146046439d37 (diff) | |
| download | coreboot-8fa8f4bdc341d3249aec5fda87f80417cb8917b3.tar.xz | |
arch/mips: provide proper cache primitives
This provides the opportunity to remove the kludge of disabling caches
altogether in the bootblock.
[pg: originally, this commit also provided automatic cache management
after loading stages, ie. flush dcache, so code ends up in icache. This
is done differently in upstream, so it's left out here]
BUG=chrome-os-partner:34127, chrome-os-partner:31438
TEST=with this fix romstage, ramstage and payload are executed properly
BRANCH=none
Change-Id: I568c68d02b2cd9c1c2c9c1495ba3343c82509ccc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 95ab0f159cabf21fc100f371d451211e7d113761
Original-Change-Id: Iaf90b052073dd355ab9114e8dba9f5ef76188c94
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/232410
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9618
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/mips/include')
| -rw-r--r-- | src/arch/mips/include/arch/cache.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h index a9857414ce..8c7b6f1aeb 100644 --- a/src/arch/mips/include/arch/cache.h +++ b/src/arch/mips/include/arch/cache.h @@ -20,4 +20,33 @@ #ifndef __MIPS_ARCH_CACHE_H #define __MIPS_ARCH_CACHE_H +#include <stddef.h> +#include <stdint.h> + +#define get_icache_line() __get_line_size($16, 1, 19, 3) +#define get_dcache_line() __get_line_size($16, 1, 10, 3) +#define get_L2cache_line() __get_line_size($16, 2, 20, 4) + +#define CACHE_TYPE_SHIFT (0) +#define CACHE_OP_SHIFT (2) +#define CACHE_TYPE_MASK (0x3) +#define CACHE_OP_MASK (0x7) + +/* Cache type */ +#define ICACHE 0x00 +#define DCACHE 0x01 +#define L2CACHE 0x03 + +/* Cache operation*/ +#define WB_INVD 0x05 + +#define CACHE_CODE(type, op) ((((type) & (CACHE_TYPE_MASK)) << \ + (CACHE_TYPE_SHIFT)) | \ + (((op) & (CACHE_OP_MASK)) << (CACHE_OP_SHIFT))) + +/* Perform cache operation on cache lines for target addresses */ +void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation); +/* Invalidate all caches: instruction, data, L2 data */ +void cache_invalidate_all(uintptr_t start, size_t size); + #endif /* __MIPS_ARCH_CACHE_H */ |