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authorJulius Werner <jwerner@chromium.org>2017-04-17 18:16:39 -0700
committerJulius Werner <jwerner@chromium.org>2017-05-30 22:19:50 +0200
commitcd6b22f9a02a7e21b39cc8a68d7ceb2f90a0815b (patch)
treea434d0931f97f532dc68615e22fec39dd217bec2 /src/arch/mips/include
parenta92851939cffcfa11d3abf80cc910a43bb48e6b0 (diff)
downloadcoreboot-cd6b22f9a02a7e21b39cc8a68d7ceb2f90a0815b.tar.xz
arch: Unify basic cache clearing API
Caching is a very architecture-specific thing, but most architectures have a cache in general. Therefore it can be useful to have a generic architecture-independent API to perform simple cache management tasks from common code. We have already standardized on the dcache_clean/invalidate naming scheme that originally comes from ARM in libpayload, so let's just do the same for coreboot. Unlike libpayload, there are other things than just DMA coherency we may want to achieve with those functions, so actually implement them for real even on architectures with cache-snooping DMA like x86. (In the future, we may find applications like this in libpayload as well and should probably rethink the API there... maybe move the current functionality to a separate dma_map/unmap API instead. But that's beyond scope of this patch.) Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/arch/mips/include')
-rw-r--r--src/arch/mips/include/arch/cache.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h
index de1209a84c..d90a85f3f3 100644
--- a/src/arch/mips/include/arch/cache.h
+++ b/src/arch/mips/include/arch/cache.h
@@ -41,4 +41,11 @@ void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation);
/* Invalidate all caches: instruction, data, L2 data */
void cache_invalidate_all(uintptr_t start, size_t size);
+/* TODO: Global cache API. Implement properly once we finally have a MIPS board
+ again where we can figure out what exactly these should be doing. */
+static inline void cache_sync_instructions(void) {}
+static inline void dcache_clean_all(void) {}
+static inline void dcache_invalidate_all(void) {}
+static inline void dcache_clean_invalidate_all(void) {}
+
#endif /* __MIPS_ARCH_CACHE_H */